LPC47M192 datasheet(108/228 Pages) SMSC

108 / 228 page

SMSC DS – LPC47M192

Page 108

Rev. 03/30/05

DATASHEET

7.11.4 INTERRUPTS

The LPC47M192 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.

7.11.5 MEMORY CONFIGURATIONS

The LPC47M192 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.

7.11.6 REGISTER DEFINITIONS

7.11.6.1

Host I/F Data Register

The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the

Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the

data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register

descriptions for more information.

7.11.6.2

Host I/F Status Register

The Status register is 8 bits wide.

Table 51 shows the contents of the Status register.

Table 51 - Status Register

C/D

IBF

OBF

Status Register

This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M192 CPU.

Writable by LPC47M192 CPU. These bits are user-definable.

C/D

(Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1

= command). During a host data/command write operation, this bit is set to “1” if SA2 = 1 or reset to “0” if

SA2 = 0.

IBF

(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register.

Setting this flag activates the LPC47M192 CPU’s nIBF (MIRQ) interrupt if enabled. When the LPC47M192

CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is

no output pin associated with this internal signal.

OBF

(Output Buffer Full) - This flag is set to whenever the LPC47M192 CPU write to the output data register

(DBB). When the host system reads the output data register, this bit is automatically reset.

7.11.7 EXTERNAL CLOCK SIGNAL

The LPC47M192 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset

pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc

POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the

chip.

LPC47M192 Datasheet(PDF) 108 Page - SMSC Corporation

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