LPC47M192 datasheet(141/228 Pages) SMSC

141 / 228 page

SMSC DS – LPC47M192

Page 141

Rev. 03/30/05

DATASHEET

OFFSET

(hex)

TYPE

PCI RESET

VCC POR

VTR POR

SOFT

RESET

R/W

0x00

FAN1

R/W

0x00

FAN2

R/W

0x50

Fan Control

0x00

Fan1 Tachometer Register

0x00

Fan2 Tachometer Register

R/W

0x00

Fan1 Preload Register

R/W

0x00

Fan2 Preload Register

R/W

0x00

LED1

R/W

0x00

LED2

R/W

0x00

Keyboard Scan Code

60-7F

Reserved – reads return 0

Note 1

: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high.

Note 2

: Bits [3:2] of this register are reset (cleared) on VCC POR and PCI Reset (and VTR POR).

Note 3

: Bit 3 of this register is reset (cleared) on VCC POR and PCI Reset (and VTR POR).

Note 4

: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared.

Note 5

: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may

set

on a VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits

will be set on a VCC POR. These GPIOs cannot be used for PME wakeup when the part is under VTR power

(VCC=0).

LPC47M192 Datasheet(PDF) 141 Page - SMSC Corporation

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