LPC47M192 datasheet(143/228 Pages) SMSC

143 / 228 page

SMSC DS – LPC47M192

Page 143

Rev. 03/30/05

DATASHEET

NAME

REG OFFSET

(hex)

DESCRIPTION

PME_STS2

Default = 0x00

on VTR POR

(R/W)

PME Wake Status Register 2

This register indicates the state of the individual PME

wake sources, independent of the individual source

enables or the PME_En bit.

If the wake source has asserted a wake event, the

associated PME Wake Status bit will be a “1”.

Bit[0] GP10

Bit[1] GP11

Bit[2] GP12

Bit[3] GP13

Bit[4] GP14

Bit[5] GP15

Bit[6] GP16

Bit[7] GP17

The PME Wake Status register is not affected by Vcc

POR, SOFT RESET or PCI RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any

bit in PME Wake Status Register has no effect.

PME_STS3

Default = 0x00

on VTR POR

(R/W)

PME Wake Status Register 3

This register indicates the state of the individual PME

wake sources, independent of the individual source

enables or the PME_En bit.

If the wake source has asserted a wake event, the

associated PME Wake Status bit will be a “1”.

Bit[0] GP20

Bit[1] GP21

Bit[2] GP22

Bit[3] DEVINT_STS (status of group SMI signal for PME)

Bit[4] GP24

Bit[5] GP25

Bit[6] GP26

Bit[7] GP27

The PME Wake Status register is not affected by Vcc

POR, SOFT RESET or PCI RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any

bit in PME Wake Status Register has no effect.

LPC47M192 Datasheet(PDF) 143 Page - SMSC Corporation

LPC47M192 Datasheet(HTML) 143 Page - SMSC Corporation

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