LPC47M192 datasheet(142/228 Pages) SMSC

142 / 228 page

SMSC DS – LPC47M192

Page 142

Rev. 03/30/05

DATASHEET

The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address

Table 63 - Runtime Register Block Description

NAME

REG OFFSET

(hex)

DESCRIPTION

PME_STS

Default = 0x00

on VTR POR

(R/W)

Bit[0] PME_Status

= 0 (default)

= 1 Set when LPC47M192 would normally assert the

nIO_PME signal, independent of the state of the

PME_En bit.

Bit[7:1] Reserved

PME_Status is not affected by Vcc POR, SOFT RESET

or PCI RESET.

Writing a “1” to PME_Status will clear it and cause the

LPC47M192 to stop asserting nIO_PME, in enabled.

Writing a “0” to PME_Status has no effect.

N/A

(R)

Bits[7:0] Reserved – reads return 0

PME_EN

Default = 0x00

on VTR POR

(R/W)

Bit[0] PME_En

= 0

nIO_PME signal assertion is disabled (default)

= 1

Enables LPC47M192 to assert nIO_PME signal

Bit[7:1] Reserved

PME_En is not affected by Vcc POR, SOFT RESET or

PCI RESET

N/A

(R)

Bits[7:0] Reserved – reads return 0

PME_STS1

Default = 0x00

on VTR POR

(R/W)

PME Wake Status Register 1

This register indicates the state of the individual PME

wake sources, independent of the individual source

enables or the PME_En bit.

If the wake source has asserted a wake event, the

associated PME Wake Status bit will be a “1”.

Bit[0] Reserved (Note 7)

Bit[1] RI2

Bit[2] RI1

Bit[3] KBD

Bit[4] MOUSE

Bit[5] SPEKEY (Wake on specific key)

Bit[6] FAN_TACH1

Bit[7] FAN_TACH2

The PME Wake Status register is not affected by Vcc

POR, SOFT RESET or PCI RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any

bit in PME Wake Status Register has no effect.

LPC47M192 Datasheet(PDF) 142 Page - SMSC Corporation

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