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LPC47M192 Datasheet(PDF) 171 Page - SMSC Corporation

Part # LPC47M192
Description  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 Datasheet(HTML) 171 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 171
Rev. 03/30/05
DATASHEET
REGISTER
ADDRESS
DESCRIPTION
Power Mgmt
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
0x23 R/W
Bit[0] FDC (See Note in the “FDC Power
Management” section)
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6] MPU-401
Bit[7] Reserved (read as 0)
For each bit above (except Reserved)
= 0 Intelligent Pwr Mgmt off
= 1 Intelligent Pwr Mgmt on
OSC
Default = 0x44, on
on VCC POR,
VTR POR and
PCI RESET
0x24 R/W
Bit[0] Reserved
Bit [1] PLL Control
= 0 PLL is on (backward Compatible)
= 1 PLL is off
Bits[3:2] OSC
= 01Osc is on, BRG clock is on.
= 10Same as above (01) case.
= 00Osc is on, BRG Clock Enabled.
= 11Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0 12-Bit Address Qualification
= 1 16-Bit Address Qualification
Note
: For normal operation, bit 6 should be set.
Bit[7] Reserved
Chip Level
Vendor Defined
0x25
Reserved - Writes are ignored, reads return 0.
Configuration
Address Byte 0
Default
=0x2E (Sysopt=0)
=0x4E (Sysopt=1)
on VCC POR and
PCI RESET
0x26
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
See Note 1
Configuration
Address Byte 1
Default = 0x00
on VCC POR and
PCI RESET
0x27
Bit[7:0] Configuration Address Bits [15:8]
See Note 1
Default = 0x00
on VCC POR,
SOFT RESET and
PCI RESET
0x28
Bits[7:0] Reserved - Writes are ignored, reads return
0.
Chip Level
Vendor Defined
0x29
Reserved - Writes are ignored, reads return 0.



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