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LPC47M192 Datasheet(PDF) 174 Page - SMSC Corporation

Part # LPC47M192
Description  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 Datasheet(HTML) 174 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 174
Rev. 03/30/05
DATASHEET
LOGICAL DEVICE
REGISTER
ADDRESS
DESCRIPTION
DMA Channel Select
Default = 0x02 or 0x04
(Note 4)
on VCC POR, VTR POR,
PCI RESET and
SOFT RESET
(0x74,0x75)
Only 0x74 is implemented for FDC and Parallel
port. 0x75 is not implemented and ignores
writes and returns zero when read. Refer to
DMA Channel Configuration.
32-Bit
Memory
Space
Configuration
(0x76-0xA8)
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Logical Device
(0xA9-0xDF)
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Logical
Device
Configuration
(0xE0-0xFE)
Reserved – Vendor Defined (see SMSC
defined
Logical
Device
Configuration
Registers).
Reserved
0xFF
Reserved
Note 1
: A logical device will be active and powered up according to the following equation unless otherwise specified:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device’s Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the
other.
Note 2
: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O
map, then read or write is not valid and is ignored.
Note 3
: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 4
: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device
3 and 5 is 0x04.



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