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LPC47M192 Datasheet(PDF) 178 Page - SMSC Corporation

Part # LPC47M192
Description  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 Datasheet(HTML) 178 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 178
Rev. 03/30/05
DATASHEET
9.5 SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration Registers reset to their default values only on PCI resets
generated by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers are not affected by soft
resets.
Table 70 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]
NAME
REG INDEX
DEFINITION
FDD Mode Register
Default = 0x0E
on VCC POR,
VTR POR and
PCI RESET
0xF0 R/W
Bit[0] Floppy Mode
= 0
Normal Floppy Mode (default)
= 1
Enhanced Floppy Mode 2 (OS2)
Bit[1] FDC DMA Mode
= 0
Burst Mode is enabled
= 1
Non-Burst Mode (default)
Bit[3:2] Interface Mode
= 11
AT Mode (default)
= 10
(Reserved)
= 01
PS/2
= 00
Model 30
Bit[4] FDC_SWAP
0 = Do Not Swap (default)
1 = Swap Drive 0 (nDS, nMTR pins) with Drive 1
(nDS, nMTR pins)
Bit[5] Reserved, set to zero
Bit[6] FDC Output Type Control
= 0
FDC outputs are OD12 open drain (default)
= 1
FDC outputs are O12 push-pull
Bit[7] FDC Output Control
= 0
FDC outputs active (default)
= 1
FDC outputs tri-stated
FDD Option Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
0xF1 R/W
Bit[0] Forced Write Protect
= 0
Inactive (default)
= 1
FDD nWRTPRT input is forced active when
either of the drives has been selected.
nWRTPRT (to the FDC Core) = WP (FDC SRA
register, bit 1) = (nDS0 AND Forced Write Protect)
OR (nDS1 AND Forced Write Protect) OR nWRTPRT
(from the FDD Interface) OR Floppy Write Protect
Note
:
The Floppy Write Protect bit is in the Device
Disable register.
Note
:
Boot floppy is always drive 0.
Bit[1] Reserved
Bits[3:2] Density Select
= 00
Normal (default)
= 01
Normal (reserved for users)
= 10
1 (forced to logic “1”)
= 11
0 (forced to logic “0”)
Bit[7:4] Reserved.



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