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LPC47M192 Datasheet(PDF) 173 Page - SMSC Corporation |
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LPC47M192 Datasheet(HTML) 173 Page - SMSC Corporation |
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173 / 228 page ![]() SMSC DS – LPC47M192 Page 173 Rev. 03/30/05 DATASHEET 9.4 Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports eight logical units and has eight sets of logical device registers. The eight logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard Controller, game port, Runtime Registers and MPU-401. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below. Table 66 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS DESCRIPTION Activate (Note1) Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET (0x30) Bits[7:1] Reserved, set to zero. Bit[0] = 1 Activates the logical device currently selected through the Logical Device # register. = 0 Logical device currently selected is inactive Logical Device Control (0x31-0x37) Reserved – Writes are ignored, reads return 0. Logical Device Control (0x38-0x3F) Vendor Defined - Reserved - Writes are ignored, reads return 0. Memory Base Address (0x40-0x5F) Reserved – Writes are ignored, reads return 0. I/O Base Address (Note 2) (see Device Base I/O Address Table) Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 67 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. Interrupt Select Defaults : 0x70 = 0x00 or 0x06 (Note 3) on VCC POR, VTR POR, PCI RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, PCI RESET and SOFT RESET (0x70,0x72) 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible). (0x71,0x73) Reserved - not implemented. These register locations ignore writes and return zero when read. |
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