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LPC47M192 Datasheet(PDF) 183 Page - SMSC Corporation

Part # LPC47M192
Description  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 Datasheet(HTML) 183 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 183
Rev. 03/30/05
DATASHEET
Table 75 - PME, Logical Device A [Logical Device Number = 0x0A]
NAME
REG INDEX
DEFINITION
CLOCKI32
Default = 0x00
on VTR POR
0xF0
(R/W)
Bit[0] (CLK32_PRSN)
0=32kHz clock is connected to the CLKI32
pin (default)
1=32kHz clock is not connected to the CLKI32
pin (pin is grounded)
Bit[1] SPEKEY_EN. This bit is used to turn the logic for
the “wake on specific key” feature on and off. It will
disable the 32kHz clock input to the logic when turned
off. The logic will draw no power when disabled.
0= “Wake on specific key” logic is
on (default)
1= “Wake on specific key” logic is off
Bits[7:2] are reserved
Note:
The registers located in Logical Device A are runtime registers.
Table 76 - MPU-401 [Logical Device Number = 0x0B]
NAME
REG INDEX
DEFINITION
MPU-401
Primary
Base I/O Address
High Byte
Default = 0x03
on
PCI
RESET,
SOFT RESET, VCC
POR and VTR POR
0x60 R/W
Bit[0] A8
Bit[1] A9
Bit[2] A10
Bit[3] A11
Bit[4] “0”
Bit[5] “0”
Bit[6] “0”
Bit[7] “0”
MPU-401
Primary
Base I/O Address
Low Byte
Default = 0x30
on
PCI
RESET,
SOFT RESET, VCC
POR and VTR POR
0x61 R/W
Bit[0] “0”
Bit[1] A1
Bit[2] A2
Bit[3] A3
Bit[4] A4
Bit[5] A5
Bit[6] A6
Bit[7] A7
Note:
Bit[0] must be “0”.



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