ADF4371 datasheet(42/46 Pages) AD

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ADF4371

Preliminary Technical Data

Rev. PrI | Page 42 of 46

RF SYNTHESIZER—A WORKED EXAMPLE

Use the following equations to program the ADF4371 synthesizer:

(

)

Divider

MOD1

MOD2

FRAC2

FRAC1

INT

PFD

OUT

(7)

where:

RFOUT is the RF output frequency.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD1 is the fixed 25-bit modulus.

MOD2 is the auxiliary modulus.

RF Divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(8)

where:

REFIN is the reference frequency input.

D is the REFIN doubler bit.

R is the REF reference division factor.

T is the reference divide by 2 bit (0 or 1).

For example, in a universal mobile telecommunication system

(UMTS) where a 2112.8 MHz RF frequency output (RFOUT) is

required, a 122.88 MHz reference frequency input (REFIN)

is available. Note that the ADF4371 VCO operates in the

frequency range of 4 GHz to 8 GHz. Therefore, the RF divider of 2

must be used (VCO frequency = 4225.6 MHz, RFOUT =

VCO frequency/RF divider = 4225.6 MHz/2 = 2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 16).

In this example, the 122.88 MHz reference signal is divided by 2

to generate fPFD of 61.44 MHz. The desired channel spacing is

200 kHz.

Figure 16. Loop Closed Before Output Divider

The worked example follows:

•

N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =

68.7760416666666667

•

INT = int(VCO frequency/fPFD) = 68

•

FRAC = 0.7760416666666667

•

MOD1 = 33,554,432

•

FRAC1 = int(MOD1 × FRAC) = 26,039,637

•

Remainder = 0.3333333333 or 1/3

•

MOD2 = fPFD/GCD(fPFD, fCHSP) =

61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536

•

FRAC2 = Remainder × 1536 = 512

From Equation 8,

fPFD = (122.88 MHz × (1 + 0)/2) = 61.44

MHz

(x)

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/225))/2

(9)

where:

INT = 68

FRAC1 = 26,039,637

MOD2 = 1536

FRAC2 = 512

RF Divider = 2

REFERENCE INPUT SENSITIVITY

The slew rate of the input reference signal significantly affects

the performance. The part is functional with signals of very low

amplitude down to 0.4Vpp and with slew rate 21V/us. However,

the best performance is achieved with slew rates as high as

1000V/us. Achieving this slew rate with sinusoidal waves

requires high amplitudes and may not be possible at low

frequencies. The jitter and phase noise performance of

ADF4371 is given in Figures xx and xx for PFD frequencies 250

MHz and 100 MHz respectively.

A high performance square wave signal with a high slew rate is

recommended as the reference input signal to achieve the best

performance.

fPFD

PFD

VCO

DIVIDER

÷2

RFOUT

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