ADF4371 datasheet(28/46 Pages) AD

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ADF4371

Preliminary Technical Data

Rev. PrI | Page 28 of 46

Bits

Bit Name

Description

Reset

Access

MUXOUT_EN

Muxout Enable. Set to 0 if using the SDO for register readback

0x0

R/W

0: Data pin used for readback.

1: Muxout pin used for readback.

LEV_SEL

Muxout Level Select. Select the voltage level of the logic at the Muxout.

0x1

R/W

0: 1.8V logic.

1: 3.3V logic.

[1:0]

R_WORD[9:8]

10 Bit R-Counter

0x0

R/W

Address: 0x22, Reset: 0x00, Name: REG0022

Table 32. Bit Descriptions for REG0022

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

REFIN_MODE

Choose Between Single-Ended or Differential Refin

0x0

R/W

0: Single-Ended Refin.

1: Differential Refin.

REF_DOUB

Reference Doubler. Controls the reference doubler block.

0x0

R/W

0: Doubler Disabled.

1: Doubler Enabled.

RDIV2

RDIV2. Controls the reference divide-by-2 clock. This feature can be used to provide a 50%

duty cycle signal to the PFD

0x0

R/W

0: RDIV2 Disabled.

1: RDIV2 Enabled.

[3:0]

RESERVED

Reserved.

0x0

Address: 0x23, Reset: 0x00, Name: REG0023

Table 33. Bit Descriptions for REG0023

Bits

Bit Name

Description

Reset

Access

[7:6]

RESERVED

Reserved.

0x0

[5:4]

CLK_DIV_MODE

CLK Div Mode. Set to 0b10 to enable phase resync. When not using phase

resync set to 0b00.

0x0

R/W

0: CLK Div Off.

10: Resync Enabled.

[3:2]

RESERVED

Reserved.

0x0

TRACKING_FILTER_MUX_SEL

0x0

R/W

0: Normal: Tracking filter coefficients set automatically.

1: Tracking Filter coefficients set manually from SPI; band_sel_x2,

band_sel_x4.

RESERVED

Reserved.

0x0

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