ADF4371 datasheet(17/46 Pages) AD

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Preliminary Technical Data

ADF4371

Rev. PrI | Page 17 of 46

Figure 12. VCO Sensitivity, KV vs. Frequency VCC_VCO = 5 V

Figure 13. VCO Sensitivity, KV vs. Frequency VCC_VCO = 3.3 V

OUTPUT STAGE

The RF8P and RF8N pins of the ADF4371 connect to

the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 13. In this scheme,

the ADF4371 contains internal 50 Ω resistors connected to

the VCC_X1 pin. To optimize the power dissipation vs. the

output power requirements, the tail current of the differential

pair is programmable using Bits[1:0] in Register 25. Four

current levels can be set. These levels give approximate output

power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm,

respectively. Levels of −4 dBm, −1 dBm, +2 dBm can be

achieved by ac coupling into a 50 Ω load. A +5 dBm level

requires an external shunt inductor to VCCX1. Note that an

inductor has a narrower operating frequency than a 50 Ω

resistor. For accurate power levels, refer to the Typical

Performance Characteristics section. Add an external shunt

inductor to provide higher power levels; however, this is less

wideband than the internal bias only. Terminate the unused

complementary output with a circuit similar to the used output.

Figure 13. Output Stage

The doubled VCO output (8 GHz to 16 GHz) is available on the

RF16 pin, which can be directly connected to the next circuit.

The quadrupled output is available on the RF32P/N pins, which

can also be directly connected to the next circuit. RFAUX8P/N

provides the same functionality as the RF8P/N output, but can

also output the divided RF8 frequency or alternatively the VCO

frequency if desired.

DOUBLER

Figure 14. Doubler Output Stage

The VCO frequency multiplied by 2 is available at the RF16P/N

pins. This output can be powered down when not in use, and

the pins RF16P/N can be left open if unused.

There is an automatic tracking filter which suppresses the VCO

and other unwanted frequency products, which ensures the

doubled output is maximized, and VCO and 3 x VCO

frequencies are suppressed regardless of the output frequency.

Suppression of < 50 dB is typical. The optimum values are set

automatically by the auto tracking when it is enabled using Bit-1

in Register 23.

In any case, it is possible to set coefficients manually (for

example when both quadrupler and doubler are enabled

together). The settings for optimum output power, phase noise

and harmonic rejection are given in Table 6.

Table 6: Filter and Bias Setting for Doubled Output

Frequency (GHz)

Filter

Bias

< 8.4

8.4 - 9.4

9.4 - 10

10 - 11.5

11.5 - 12.2

12.2 - 13.7

VCO

RF8P

VCCX1

50Ω

BUFFER/

DIVIDE BY

1/2/4/8/

16/32/64

RF8N

VCCX1

×2

RF16P

RF16N

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