ADF4371 datasheet(7/46 Pages) AD

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Preliminary Technical Data

ADF4371

Rev. PrI | Page 7 of 46

DIGITAL LOGIC TIMING

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SPI TIMING

See Figure 2, 3 and 4

SCLK Frequency

fSCLK

MHz

SCLK Period

tSCLK

SCLK Pulse Width High

tHIGH

SCLK Pulse Width Low

tLOW

SDIO Setup Time

tDS

SDIO Hold Time

tDH

SCLK Falling Edge to SDIO Valid

Propagation Delay

tACCESS

CSB Rising Edge to SDIO High-Z

CSB Fall to SCLK Rise Setup Time

SCLK Fall to CSB Rise Hold Time

Timing Diagrams

Figure 2. SPI Timing, MSB First (Upper) and LSB First (Lower)

Figure 3. SPI Write Operation Timing

Figure 4. SPI Read Operation Timing

Figure 5. 3-wire, MSB first, Descending Data, Streaming

SCLK

SDIO

R/W

A0 D7 D61

D1 D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

CSB

A14 A13

SCLK

SDIO

R/W

D61

D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

CSB

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

CSB

A13

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

tACCESS

CSB

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