ADF4371 datasheet(16/46 Pages) AD

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ADF4371

Preliminary Technical Data

Rev. PrI | Page 16 of 46

FRAC2 = [(N − INT) × 225 − FRAC1)] × MOD2

(5)

The FRAC2 and MOD2 fraction result in outputs with zero

frequency error for channel spacings when

fPFD/GCD(fPFD, fCHSP) = MOD2 < 16,383

(6)

where:

fPFD is the frequency of the phase frequency detector.

fCHSP is the desired channel spacing.

GCD is a greatest common divisor function.

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 39-bit resolution

modulus.

INT N Mode

When FRAC1 and FRAC2 are equal to 0, the synthesizer

operates in integer-N mode. It is recommended that the

SD_EN_FRAC0 bit in REG2B, DB0 be set to 1. This disables the

Sigma Delta Modulators which gives an improvement in the in-

band phase noise, and reduces any additional signal delta noise.

R Counter

The 10-bit R counter allows the input reference frequency

(REFP/N) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure below is a simplified schematic

of the phase frequency detector. The PFD includes a fixed delay

element that sets the width of the anti-backlash pulse. This

pulse ensures that there is no dead zone in the PFD transfer

function and provides a consistent reference spur level. Set the

phase detector polarity to positive on this device because of the

positive tuning of the VCO.

PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4371 allows the user to access

various internal points on the chip. Figure below shows the

MUXOUT section in block diagram form.

MUXOUT Schematic

DOUBLE BUFFERS

The following settings in the ADF4371 are double buffered: main

fractional value (FRAC1), auxiliary modulus value (MOD2),

auxiliary fractional value (FRAC2), reference doubler, reference

divide by 2 (RDIV2), R counter value, and charge pump current

setting. Two events must occur before the ADF4371 uses a new

value for any of the double buffered settings. First, the new value

must latch into the device by writing to the appropriate register,

and second, a new write to Register 10 must be performed.

For example, to ensure that the modulus value loads correctly,

every time that the modulus value updates, Register 10 must be

written to.

VCO

The VCO core in the ADF4371 consists of four separate VCOs,

each of which uses 256 overlapping bands, which allows the

device to cover a wide frequency range without large VCO

sensitivity (KV) and without resultant poor phase noise and

spurious performance.

The correct VCO and band are chosen automatically by the

VCO and band select logic whenever Register 10 is updated and

automatic calibration is enabled. The VCO VTUNE is disconnected

from the output of the loop filter and is connected to an internal

reference voltage.

The R counter output is used as the clock for the band select

logic. After band selection, normal PLL action resumes. The

nominal value of KV is 50 MHz/V when the N divider is driven

from the VCO output, or the KV value is divided by D. D is

the output divider value if the N divider is driven from the

RF output divider.

The VCO shows variation of KV as the tuning voltage, VTUNE,

varies within the band and from band to band. For wideband

applications covering a wide frequency range (and changing

output dividers), a value of 50 MHz/V provides the most accurate

KV, because this value is closest to the average value. Figure 12

and 13 shows how KV varies with fundamental VCO frequency

along with an average value for the frequency band. Users may

prefer this figure when using narrow-band designs.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

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