AM29BDD160G datasheet(18/80 Pages) AMD

18 / 80 page

Am29BDD160G

Table 5. Am29BDD160 Autoselect Codes (High Voltage Method)

L = Logic Low = V

IL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.

Asynchronous Read Operation (Non-

Burst)

The device has two control functions which must be

satisfied in order to obtain data at the outputs. CE#

is the power control and should be used for device

selection. OE# is the output control and should be

used to gate data to the output pins if the device is

selected. The device is power-up in an asynchronous

read mode. In the asynchronous mode the device

has two control functions which must be satisfied in

order to obtain data at the outputs. CE# is the power

control

and should be used for device selection.

OE# is the output control and should be used to gate

data to the output pins if the device is selected.

Address access time (t

ACC) is equal to the delay from

stable addresses to valid output data. The chip en-

able access time (t

CE) is the delay from the stable

addresses and stable CE# to valid data at the output

pins. The output enable access time is the delay

from the falling edge of OE# to valid data at the out-

put pins (assuming the addresses have been stable

for at least t

ACC–tOEtime).

6. Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.

Figure 1. Asynchronous Read Operation

Description

CE#

OE# WE#

A18

A11

A10

DQ7 to DQ0

Manufacturer ID:

AMD

VIO

0001h

Read Cycle 1

VIO

007Eh

Read Cycle 2

VIO

0008h

Read Cycle 3

VIO

0000h (top

boot block)

0001h (bottom

boot block)

PPB Protection

Status

VIO

0000h

(unprotected)

0001h

(protected)

CE#

CLK

ADV#

A0-A18

DQ0-DQ31

OE#

WE#

IND/WAIT#

AM29BDD160G Datasheet(PDF) 18 Page - Advanced Micro Devices

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