AM29BDD160G datasheet(28/80 Pages) AMD

28 / 80 page

Am29BDD160G

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Locking Bit is set, which indicates the device is in

Password Protection Mode, the PPB Lock Bit is also

set after a hardware reset (RESET# asserted) or a

power-up reset. The ONLY means for clearing the

PPB Lock Bit in Password Protection Mode is to issue

the Password Unlock command. Successful execution

of the Password Unlock command clears the PPB

Lock Bit, allowing for sector PPBs modifications. As-

serting RESET#, taking the device through a power-

on reset, or issuing the PPB Lock Bit Set command

sets the PPB Lock Bit back to a “1”.

If the Password Mode Locking Bit is not set, indicat-

ing Persistent Sector Protection Mode, the PPB Lock

Bit is cleared after power-up or hardware reset. The

PPB Lock Bit is set by issuing the PPB Lock Bit Set

command. Once set the only means for clearing the

PPB Lock Bit is by issuing a hardware or power-up

reset. The Password Unlock command is ignored in

Persistent Sector Protection Mode.

Hardware Data Protection

The command sequence requirement of unlock

cycles for programming or erasing provides

data protection against inadvertent writes. In

addition, the following hardware data protec-

tion measures prevent accidental erasure or

programming, which might otherwise be

caused by spurious system level signals during

CC power-up and power-down transitions, or

from system noise.

Low V

CC Write Inhibit

When V

CC is less than VLKO, the device does not

accept any write cycles. This protects data dur-

ing V

CC power-up a n d

power- down. The

command register and all internal erase/pro-

gram circuits are disabled, and the device

resets. Subsequent writes are ignored until V

is greater than V

LKO. The system must provide

the proper signals to the control pins to prevent

unintentional writes when V

CC is greater than

LKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#,

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

OE# = V

IL, CE# = VIH, or WE# = VIH. To initiate

a write cycle, CE# and WE# must be a logical

zero (V

IL) while OE# is a logical one (VIH).

Power-Up Write Inhibit

If WE# = CE# = V

IL and O E# = VIH during

power-up, the device does not accept com-

mands on the rising edge of WE#. The internal

state machine is automatically reset to reading

array data on power-up.

CC and VIO Power-up And Power-down

Sequencing

The device imposes no restrictions on V

CC and

IO power-up or power-down sequencing. As-

serting RESET# to V

IL is required during the

entire V

CC and VIO power sequence until the re-

spective supp lies reach their op erating

voltages. Once, V

CC and VIO attain their respec-

tive operating voltages, de-assertion of

RESET# to V

IH is permitted.

Table 12. Sector Addressees for Top Boot Sector Devices (Sheet 1 of 2)

Sector

Sector Group

x16 Address Range

(A18:A-1)

x32 Address Range

(A18:A0)

Sector Size

(Kwords)

Bank 1

(Note 2)

SA0 (Note 1)

SG0

00000h-00FFFh

00000h-007FFh

SA1

SG1

01000h-01FFFh

00800h-00FFFh

SA2

SG2

02000h-02FFFh

01000h-017FFh

SA3

SG3

03000h-03FFFh

01800h-01FFFh

SA4

SG4

04000h-04FFFh

02000h-027FFh

SA5

SG5

05000h-05FFFh

02800h-02FFFh

SA6

SG6

06000h-06FFFh

03000h-037FFh

SA7

SG7

07000h-07FFFh

03800h-03FFFh

SA8

08000h-0FFFFh

04000h-07FFFh

SA9

SG8

10000h-17FFFh

08000h-0BFFFh

SA10

18000h-1FFFFh

0C000h-0FFFFh

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