AM29BDD160G datasheet(46/80 Pages) AMD

46 / 80 page

Am29BDD160G

Legend:

BA = Address of the bank that is being switched to autose-

lect mode, is in bypass mode, or is being erased. Deter-

mined by A18 and A17, see Tables 11 and 12 for more

detail.

PA = Program Address (A18:A0). Addresses latch on the

falling edge of the WE# or CE# pulse, whichever hap-

pens later

PD = Program Data (DQ31:DQ0) written to location PA.

Data latches on the rising edge of WE# or CE# pulse,

whichever happens first.

RA = Read Address (A18:A0).

RD = Read Data (DQ31:DQ0) from location RA.

SA = Sector Address (A18:A11) for verifying (in autoselect

mode), erasing, or applying security commands.

WD = Write Data. See “Configuration Register” definition

X= Don’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles

are write operations.

4. During unlock cycles, (lower address bits are 555 or

2AAh as shown in table) address bits higher than A11

(except where BA is required) and data bits higher than

DQ7 are don’t cares.

Table 19. Memory Array Command Definitions (x32 Mode)

Command (Notes)

Cycles

Bus Cycles (Notes 1–4)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (5)

Reset (6)

XXX

Autoselec

t (7)

Manufactur

er ID

555

2AA

555

(BA)X0

Device ID

(11)

555

2AA

555

(BA)X0

(BA)X0E

(BA)X0F

00/

Program

555

2AA

555

Chip Erase

555

2AA

555

2AA

555

Sector Erase

555

2AA

555

2AA

Program/Erase

Suspend (12)

Program/Erase Resume

(13)

CFI Query (14, 15)

Accelerated Program

(16)

Configuration Register

Verify (15)

555

2AA

(BA)55

(BA)XX

Configuration Register

Write (17)

555

2AA

555

Unlock Bypass Entry

(18)

555

2AA

555

Unlock Bypass Program

(18)

Unlock Bypass Erase

(18)

Unlock Bypass CFI (14,

18)

Unlock Bypass Reset

(18)

AM29BDD160G Datasheet(PDF) 46 Page - Advanced Micro Devices

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