AM29BDD160G datasheet(56/80 Pages) AMD

56 / 80 page

Am29BDD160G

additional sectors are selected for erasure, the entire

time-out also applies after each additional sector

erase command. When the time-out is complete,

DQ3 switches from “0” to “1.” The system may ig-

nore DQ3 if the system can guarantee that the time

between additional sector erase commands will al-

ways be less than 50 µs. See also the Sector Erase

Command section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device

has accepted the command sequence, and then read

DQ3. If DQ3 is “1”, the internally controlled erase

cycle has begun; all further commands (other than

Erase Suspend) are ignored until the erase operation

is complete. If DQ3 is “0”, the device will accept ad-

ditional sector erase commands. To ensure the

command has been accepted, the system software

should check the status of DQ3 prior to and following

each subsequent sector erase command. If DQ3 is

high on the second status check, the last command

might not have been accepted. Table 23 shows the

outputs for DQ3.

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See DQ5: Exceeded Timing Limits for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

Table 23. Write Operation Status

Operation

DQ7

(Note 2)

DQ6

DQ5 (Note

DQ3

DQ2 (Note

RY/BY#

Standard

Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase

Suspend

Mode

Reading within Erase Suspended

Sector

No toggle

N/A

Toggle

Reading within Non-Erase

Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

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