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AM29BDD160G Datasheet(PDF) 63 Page - Advanced Micro Devices |
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AM29BDD160G Datasheet(HTML) 63 Page - Advanced Micro Devices |
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63 / 80 page  Am29BDD160G 61 AC CHARACTERISTICS Burst Mode Read Note: See Product Selector Guide for minimum initial clock delay prior to initial valid data. t IACC may also be calculated using the following formula: t IACC = (clock delays) x (clock period) + tBACC. Parameter Description Speed Options Unit JEDEC Std. 54D 64C 65A tIACC Asynchronous Access Time ADV# Valid Clock to Output Delay (See Note) Max 54 64 67 ns tBACC Burst Access Time Valid Clock to Output Delay Max 9 FBGA 9.5 PQFP 10 FBGA 10 PQFP 17 ns tADVCS ADV# Setup Time to Rising (Falling) Edge of CLK Min 4 5 7 ns tADVCH ADV# Hold Time Min 2 ns tADVP ADV# Pulse Width Min 15 15 18 ns tBDH Data Hold Time from Next Clock Cycle Max 4 ns tDVCH Valid Data Hold from CLK Min 2 3 3 ns tDIND CLK to Valid IND/WAIT# Max 9 FBGA 9.5 PQFP 10 FBGA 10 PQFP 17 ns tINDH IND/WAIT# Hold from CLK Min 2 3 3 ns tIACC CLK to Valid Data Out, Initial Burst Access Max 54 60 68 ns tCLK CLK Period Min 15 18 25 ns Max 60 tCR CLK Rise Time Max 3 ns tCF CLK Fall Time Max 3 ns tCH CLK High Time Min 2.5 2.5 3 ns tCL CLK Low Time Min 2.5 2.5 3 ns tDS Data Setup to WE# Rising Edge Min 15 15 16 ns tDH Data Hold from WE# Rising Edge Min 2 ns tAS Address Setup to Falling Edge of WE# Min 0 ns tAH Address Hold from Falling Edge of WE# Min 25 30 33 ns tCS CE# Setup Time Min 3 ns tCH CE# Hold Time Min 3 ns tACS Address Setup Time to CLK (See Note) Min 5 6 7 ns tACH Address Hold Time from ADV# Rising Edge (See Note) Min 1 2 2 ns tOE Output Enable to Output Valid Max 20 ns tDF tOEZ Output Enable to Output High Z Min 2 3 3 ns Max 10 15 17 tEHQZ tCEZ Chip Enable to Output High Z Max 10 15 17 ns tCES CE# Setup Time to Clock Min 4 5 6 ns |
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