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ESP8266 Datasheet(PDF) 30 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.

Part # ESP8266
Description  General Purpose Input/Output Interface (GPIO)
PDF  117 Pages
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Manufacturer  ESPRESSIF [ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.]
Direct Link  https://www.espressif.com/
Logo ESPRESSIF - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.

ESP8266 Datasheet(HTML) 30 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.

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4. SPI Communication User Guide
4.2.2. Master SPI Communication Format Supported by Current API
The API function of ESP8266 SPI has two master initialization modes: one supports most
of the general signals and the other is designed for driving a colored LCD screen. The
device needs non-standard 9 bits SPI communication format. Please refer to
Section 4.4.1
for detailed information.
4.3. ESP8266 SPI Slave Protocol Format
4.3.1. SPI Slave Clock Polarity Configuration Requirement
The master device clock polarity configuration of ESP8266 SPI slave communication
should be set with idle low power , rising edge sampling and falling edge data
transformation. Please make sure to keep low power for CS in a 16’s reading/writing
process. If the CS power is raised to high level while sending, the internal state of slave will
be reset.
4.3.2. Communication Format Supported by Slave SPI
Slave ESP8266SPI communication format is almost the same as that of the master mode,
i.e. command+address+read/write data, but the slave read/write operation has its
hardware command and undeletable address, which is,
•
Command: a must; length: 3 ~ 16 bits; master output and slave input (MOSI).
•
Address: a must; length: 1 ~ 32 bits master output and slave input (MOSI).
•
Read/write data: optional; length: 0 ~ 512 bits (64 Bytes); master output and slave
input (MOSI) or master input and slave output (MISO).
4.3.3. Command Definition Supported by Slave SPI
The length of slave receiving command should at least be 3 bits. For low 3 bits, there are
hardware reading and writing operation, which is,
•
010 (slave receiving) : Write the data sent by master into the register of slave data
caching via MOSI, i.e. SPI_FLASH_C0 to SPI_FLASH_C15.
•
011 (slave sending): Send the data in the register of slave data caching (from
SPI_FLASH_C0 to SPI_FLASH_C15) to master via MOSI.
•
110 (slave receiving and sending): Send slave data caching to MISO and write the
master data in MOSI into data caching SPI_FLASH_C0 to SPI_FLASH_C15.
⚠ Notice:
Other vales are used to read and write the status register of slave SPI, SPI_FLASH_STATUS. Please do not
use it because the difference between communication format and data caching reading/writing might lead to
slave read/write error.
Espressif
! /!
22 104
2017.05



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