ESP8266 datasheet(94/117 Pages) ESPRESSIF

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11. UART Introduction

To enable interrupt:

In UART_INT_ENA register,

#deﬁne UART_PARITY_ERR_INT_ENA (BIT(2)) //Parity error enable interrupt bit, 1:enable;

0:disable

#deﬁne UART_BRK_DET_INT_ENA (BIT(7)) //Terminal line error enable interrupt bit

1: enable;0: disable

#deﬁne UART_FRM_ERR_INT_ENA (BIT(3)) //Received frame error to enable interrupt bit

1: enable;0: disable

Clear interrupt status:

Clear the interrupt status bit after dealing with corresponding error.

Flow control status interrupt

Interruption status bit:

UART_CTS_CHG_INT_ST

UART_DSR_CHG_INT_ST

Deﬁnition:

When the CTS, DSR pin-line level changes, trigger this interrupt.

Application:

Generally use with ﬂow control, when the trigger the interrupt, check the corresponding

ﬂow control line status,if it’s high, stop writing to tx queue.

#deﬁne UART_CTS_CHG_INT_ST

(BIT(6))

#deﬁne UART_DSR_CHG_INT_ST

(BIT(5))

Set enable interrupt:

In UART_INT_ENA register,

#deﬁne UART_CTS_CHG_INT_ENA (BIT(6)) CTS //Line status enable interrupt bit,

1:enable;0:disable

#deﬁne UART_DSR_CHG_INT_ENA (BIT(5)) DSR //Line status enable interrupt bit,

1:enable;0:disable

Clear interrupt status:

After dealing with the corresponding error,clear the interrupt status bit.

Espressif

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2017.05

ESP8266 Datasheet(PDF) 94 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.