ESP8266 datasheet(82/117 Pages) ESPRESSIF

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10. I2S Module Description

10.2.1.5.Clock Mode

in the I2SCONF:

•

Bits16 ~ 21 are the prescaler of the input clock (I2S_CLKM_DIV_NUM).

•

Bits 22 ~ 27 are the frequency divider of the communication clock signal

(I2S_BCK_DIV_NUM).

10.2.1.6.Other Conﬁgurations

triggers the SLC transport (unit: 4 bytes).

See the deﬁnitions of

i2s_reg.h in DEMO. Other instructions will be updated.

10.2.2. Link List Conﬁguration

In the ESP8266, the DMA transfers the receive and transport packets in the SDIO to the

corresponding memory. The software will deﬁne the structure (or group) of the registration

list and cache space(s).

As shown in Figure 10-1, there is only one cache space and one registration list. Write the

ﬁrst address of the cache and other information to the registration list, and then write the

ﬁrst address of the registration list to the hardware register of the ESP8266. Therefore, the

DMA will automatically operate the SDIO and the cache space.

Figure 10-1. Registration List

Value

Description

Dual-channel

Right channel

Left channel

owner

sub_sof

5’b0

length［11:0］

size［11:0］

eof

buf_ptr [31:0]

next_link_ptr [31:0]

word 0

word 1

word 2

Field name

Description

owner

1’b0

Software operates the buffer of the current link. The MAC shouldn't use this bit.

1’b1

Hardware operates the buffer of the current link.

Espressif

! /!

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2017.05

ESP8266 Datasheet(PDF) 82 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.

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