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ESP8266 Datasheet(PDF) 90 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
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ESP8266 Datasheet(HTML) 90 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
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90 / 117 page ![]() ! 11. UART Introduction PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS); • Hardware flow control in the receive direction can configure thresholds,when the length of rx fifo is greater than the set threshold,U0RTS feet will be pulled to prevent the other party sending. Configured the thresholds of receiving flow control: The threshold related configurations are generally defined in UART_CONF1 register. #define UART_RX_FLOW_EN (BIT(23)) The 23rd bit enabled to receive flow control: 0: disable; 1: enable #define UART_RX_FLOW_THRHD 0x0000007F //Threshold, occupied 7bit, range 0 ~ 127 #define UART_RX_FLOW_THRHD_S 16 //Register offset is 16 (start from 16th bit) • Once configure enable of the flow control of sending direction configuration,the register in UART_CONF0: #define UART_TX_FLOW_EN (BIT(15)) Enable transmission flow control: 0: disable ; 1: enable • Interface: Void UART_SetFlowCtrl(uint8 uart_no,UART_HwFlowCtrl flow_ctrl,uint8 rx_thresh); e)demo hardware board connections: Need to connect the J68 (U0CTS) and J63 (U0RTS) jumper . 11.3.11.Other Interfaces TX_FIFO_LEN(uart_no) //Macro definition, the current length of the transmit queue RF_FIFO_LEN(uart_no) //Macro definition, the current length of the receiving queue 11.4. Configure Interrupt Since all interrupt events will be conducted together in the "OR" operation before being sent to the interrupt controller,UART can only generate an interrupt request each time.By polling the interrupt state function UART_INT_ST (uart_no),software can deal with multiple interrupt events in one interrupt service function(multiple if parallel statement). 11.4.1. Interrupt register Interruption registers in UART: UART_INT_RAW Interrupt the original status register UART_INT_ENA Interrupt enable register: Indicates interrupt the current enable UART UART_INT_ST Interrupt Status Register: Indicates the currently active interrupt status UART_INT_CLR Clear Interrupt register:set the corresponding bit to clear the interrupt status register Espressif ! /! 82 104 2017.05 |
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