M482 datasheet(9/401 Pages) NUVOTON

9 / 401 page

Mar 30, 2018

Page 9 of 401

Rev 1.00

NuMicro

® M480

32-bit ARM

Cortex

-M4F Microcontrolle

Figure 6.3-5 SysTick Clock Control Block Diagram ..................................................................... 295

Figure 6.3-6 Clock Output Block Diagram ................................................................................... 296

Figure 6.3-7 USB Clock Source ................................................................................................... 297

Figure 6.25-1 SPI Master Mode Application Block Diagram........................................................ 323

Figure 6.25-2 SPI Slave Mode Application Block Diagram.......................................................... 323

Figure 6.26-1 I

2C Bus Timing....................................................................................................... 325

Figure 8.3-1 Current Consumption versus Temperature in Normal Run Mode, VDD = 3.3V , All

Peripherals Disabled, PLL Source from HIRC...................................................................... 352

Figure 8.3-2 Current Consumption versus Temperature in Normal Run Mode, VDD = 3.3V , All

Peripherals Enabled, PLL Source from HIRC....................................................................... 352

Figure 8.3-3 Current Consumption versus temperature in Normal Run Mode, VDD = 3.3V , All

Peripherals Disabled, PLL Source from HXT ....................................................................... 353

Figure 8.3-4 Current Consumption versus Temperature in Normal Run Mode, VDD = 3.3V , All

Peripherals Enabled, PLL Source from HXT ........................................................................ 353

Figure 8.3-5 Current Consumption versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals

Disabled, PLL Source from HIRC ......................................................................................... 355

Figure 8.3-6 Current Consumption versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals

Enabled, PLL Source from HIRC .......................................................................................... 355

Figure 8.3-7 Current Consumption versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals

Disabled, PLL Source from HXT........................................................................................... 356

Figure 8.3-8 Current Consumption versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals

Enabled, PLL Source from HXT............................................................................................ 356

Figure 8.4-1 Typical Crystal Application Circuit ........................................................................... 363

Figure 8.4-2 Typical Crystal Application Circuit ........................................................................... 365

Figure 8.5-1 Power-up Ramp Condition ...................................................................................... 369

Figure 8.5-2 Typical Connection with Internal Voltage Reference............................................... 370

Figure 8.7-1 I

2C Timing Diagram ................................................................................................. 378

Figure 8.8-1 SPI Master Mode Timing Diagram .......................................................................... 379

Figure 8.8-2 SPI Slave Mode Timing Diagram ............................................................................ 381

Figure 8.9-1 I

2S Master Mode Timing Diagram............................................................................ 382

Figure 8.9-2 I

2S Slave Mode Timing Diagram.............................................................................. 383

Figure 8.10-1 I

2C Timing Diagram ............................................................................................... 384

Figure 8.11-1 SPI Master Mode Timing Diagram ........................................................................ 385

Figure 8.11-2 SPI Slave Mode Timing Diagram .......................................................................... 387

Figure 8.13-1 RMII Interface Timing Diagram.............................................................................. 389

Figure 8.13-2 Ethernet PHY Management Interface Timing Diagram ......................................... 390

Figure 8.14-1 SDIO Default Mode................................................................................................ 391

Figure 8.14-2 SDIO High-speed Mode ........................................................................................ 392

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