M482 datasheet(18/401 Pages) NUVOTON

18 / 401 page

Mar 30, 2018

Page 18 of 401

Rev 1.00

NuMicro

® M480

32-bit ARM

Cortex

-M4F Microcontrolle

 Configurable bit length of a transfer word from 8 to 32-bit

 Provides separate 8-level depth transmit and receive FIFO buffers

 Supports MSB first or LSB first transfer sequence

 Supports the byte reorder function

 Supports Byte or Word Suspend mode

 Supports 3-wired, no slave select signal, bi-direction interface

 PDMA operation.

SPI/I

 Up to four sets of SPI/I

2S controllers with Master/Slave mode.

 SPI/I

2S provides separate 4-level of 32-bit (or 8-level of 16-bit)

transmit and receive FIFO buffers.

SPI

 SPI can communicate at up to 96 Mbit/s

 Configurable bit length of a transfer word from 8 to 32-bit.

 MSB first or LSB first transfer sequence.

 Byte reorder function.

 Supports Byte or Word Suspend mode.

 Supports one data channel half-duplex transfer.

 Supports receive-only mode.

 Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit

audio data sizes.

 Supports PCM mode A, PCM mode B, I

2S and MSB justified data

format.

 PDMA operation.

 One set of I

2S interface with Master/Slave mode.

 Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit

word sizes.

 Two 16-level FIFO data buffers, one for transmitting and the other

for receiving.

 Supports I

2S protocols: Philips standard, MSB-justified, and LSB-

justified data format.

 Supports PCM protocols: PCM standard, MSB-justified, and LSB-

justified data format.

 PCM protocol supports TDM multi-channel transmission in one

audio sample; the number of data channel can be set as 2, 4, 6 or

 PDMA operation.

Universal Serial Control

Interface (USCI)

 Two sets of USCI,configured as UART, SPI or I

2C function.

 Supports single byte TX and RX buffer mode

UART

 Supports one transmit buffer and two receive buffers for data

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