M482 datasheet(19/401 Pages) NUVOTON

19 / 401 page

Mar 30, 2018

Page 19 of 401

Rev 1.00

NuMicro

® M480

32-bit ARM

Cortex

-M4F Microcontrolle

payload.

 Supports hardware auto flow control function and programmable

flow control trigger level.

 9-bit Data Transfer.

 Baud rate detection by built-in capture event of baud rate generator.

 Supports wake-up function.

 PDMA operation.

SPI

 Supports Master or Slave mode operation.

 Supports one transmit buffer and two receive buffer for data

payload.

 Supports additional receive/transmit 16 entries FIFO for data

payload.

 Configurable bit length of a transfer word from 4 to 16-bit (SPI Quad

transmission only supports 8 to 16-bit of word length).

 Supports MSB first or LSB first transfer sequence.

 Supports Word Suspend function.

 Supports 3-wire, no slave select signal, bi-direction interface.

 Supports wake-up function: input slave select transition.

 PDMA operation.

 Supports master and slave device capability.

 Supports one transmit buffer and two receive buffer for data

payload.

 Communication in standard mode (100 kbps), fast mode (up to 400

kbps), and Fast mode plus (1 Mbps).

 Supports 10-bit mode.

 Supports 10-bit bus time out capability.

 Supports bus monitor mode.

 Supports power-down wake-up by data toggle or address match.

 Supports multiple address recognition.

 Supports device address flag.

 Programmable setup/hold time.

Controller Area Network

(CAN)

 Two sets of CAN 2.0B controllers.

 Each supports 32 Message Objects; each Message Object has its

own identifier mask.

 Programmable FIFO mode (concatenation of Message Object).

 Disabled Automatic Re-transmission mode for Time Triggered CAN

applications.

 Supports power-down wake-up function.

Secure Digital Host

Controller (SDHC)

 Two sets of Secure Digital Host Controllers, compliant with SD

Memory Card Specification Version 2.0.

M482 Datasheet(PDF) 19 Page - Nuvoton Technology Corporation

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