A4964 datasheet(32/92 Pages) ALLEGRO

32 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

When the MOSFET reaches the fully on state, the gate drive

output changes from current drive to voltage drive to hold the

MOSFET in the on state.

A high-side MOSFET is considered to be in the fully on state

when the drain-source voltage, VDS (= VBB – VSx), drops below

the programmed VDS threshold voltage, VDST.

A low-side MOSFET is considered to be in the fully on state

when the drain-source voltage, VDS (= VSx – VGND), drops below

the programmed VDS threshold voltage, VDST.

When a gate drive is commanded to turn off in slew control

mode, a current, IF1 (defined by IF1[3:0]) is sinked to the relevant

gate drive output for a duration, tFS (defined by TFS[3:0]).

These parameters should typically be set to quickly discharge

the MOSFET input capacitance such that the gate-source voltage

drops to close to the Miller voltage of the MOSFET. The drain-

source voltage of the MOSFET will not start to change until the

gate-source voltage reaches this level. After this time, the current

sourced on the gate drive output is set to a value of IF2 (as defined

by IF2[3:0]) and remains at this value while the MOSFET transi-

tions through the Miller region. IF2 should be selected to achieve

the required slew rate of the drain-source voltage by setting the

discharge time of the drain-gate (Miller) capacitor.

When the MOSFET reaches the fully off state the gate drive

output changes from current drive to voltage drive to hold the

MOSFET in the off state.

A high-side MOSFET is considered to be in the fully off state

when the drain-source voltage of its complementary low-side

MOSFET, VDS (= VSx – VGND), drops below the programmed

VDS threshold voltage, VDST.

VGS

High-Side

VGS

Low-Side

Min

tDEAD

Min

tDEAD

VTO

Figure 15: Minimum Dead Time

A low-side MOSFET is considered to be in the fully off state

when the drain-source voltage of its complementary high-side

MOSFET, VDS (= VBB – VSx), drops below the programmed VDS

threshold voltage, VDST.

DEAD TIME

To prevent shoot-through (transient cross-conduction) in any

phase of the power MOSFET bridge, it is necessary to have a

dead-time delay between a high- or low-side turn off and the next

complementary turn-on event. The potential for cross-conduction

occurs when any complementary high-side and low-side pair of

MOSFETs is switched at the same time, for example, at the PWM

switch point. In the A4964, the dead time for all three phases is

set by the contents of the DT[5:0] bits. These six bits contain a

positive integer that determines the dead time by division from

the system clock.

The dead time is defined as:

tDEAD = n × 50 ns

where n is a positive integer defined by DT[5:0] and tDEAD has a

minimum value of 100 ns.

For example, when DT[5:0] contains [01 1000] (= 24 in decimal),

then tDEAD = 1.2 µs, typically.

The accuracy of tDEAD is determined by the accuracy of the sys-

tem clock as defined in the electrical characteristics table. A value

of 0, 1, or 2 in DT[5:0] will set the minimum dead time of 100 ns.

The value of the dead time should be selected such that the gate-

source voltage of any pair of complementary MOSFETs is never

above the threshold voltage for both MOSFET at the same time

as shown in Figure 15. This applies in either the slew control

mode or the switch mode. In the slew control mode, the dead time

must be increased to accommodate the extended switching times.

PWM FREQUENCY

In all control modes, the base frequency of the bridge PWM

signal is fixed by the value of the base PWM period, tPW. This

base frequency can be altered by the frequency dither function

described below.

The PWM waveforms applied to each phase of the bridge can

be aligned in two ways selected by the PMD bit. When PMD is

set to 0, the bridge is in center-aligned mode and the three-phase

PWM waveforms are centered about a common point in time,

as shown in Figure 10a. When PMD is set to 1, the bridge is in

edge-aligned mode and the three-phase PWM waveforms all

change from low to high at the same time as shown in Figure 10b.

In both modes, the period of the PWM frequency is set by the

PW[5:0] variable. The six bits of PW contain a positive integer

that determines the PWM period derived by division from the

system clock.

A4964 Datasheet(PDF) 32 Page - Allegro MicroSystems

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