A4964 datasheet(82/92 Pages) ALLEGRO

82 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LAYOUT RECOMMENDATIONS

Careful consideration must be given to PCB layout when design-

ing high-frequency, fast-switching, high-current circuits:

• The two ground terminals of the QFN (EV) package, both

designated GND, are internally connected, but must also be

connected together on the PCB close to the device for correct

operation. This common point should return separately to the

negative side of the motor supply filtering capacitor. This will

minimize the effect of switching noise on the device logic and

analog reference.

• The ground terminal of the QFP (JP) package should return

separately to the negative side of the motor supply filtering

capacitor.

• The exposed thermal pad should be connected to the GND

terminals.

• Minimize stray inductance by using short, wide copper tracks

at the drain and source terminals of all power MOSFETs and

the input power bus. Particular care should be taken around

the common source of the low-side power MOSFETs and the

sense resistor. This will minimize voltages induced by fast

switching of large load currents.

• Consider the addition of small (100 nF) ceramic decoupling

capacitors across the source and drain of the power MOSFETs

to limit fast transient voltage spikes caused by track inductance.

• Keep the gate discharge return connections Sx as short as

possible. Any inductance on these tracks will cause negative

transitions on the corresponding A4964 terminals, which may

exceed the absolute maximum ratings. If this is likely, consider

the use of clamping diodes to limit the negative excursion on

these terminals with respect to the GND terminals.

• Decoupling for the supply should be provided by typically

a 10 µF low ESR electrolytic capacitor and 100 nF ceramic

capacitor in parallel. These should be connected between

VBB and GND. The ceramic capacitor in particular should be

mounted as close to the A4964 terminals as possible.

• The VREG capacitor should be connected between VREG and

GND as close to the A4964 terminals as possible. For larger

values of capacitance, a low ESR electrolytic capacitor may be

used with a ceramic capacitor greater than 100 nF in parallel.

In this case, the ceramic capacitor in particular should be

mounted as close to the A4964 terminals as possible.

• The bootstrap capacitors should be mounted close to the

associated terminals of the A4964.

• Gate charge drive paths and gate discharge return paths may

carry a large transient current pulse. Therefore the traces from

GHx, GLx, and Sx (x = A, B or C) should be as short and wide

as possible to reduce the track inductance.

• The inputs to the sense amplifier, CSP and CSM, should take

the form of independent tracks directly to the terminals of the

sense resistor, and for best results should be matched in length

and route.

• A low-cost diode can be placed in the connection to VBB

to provide reverse battery protection. In reverse battery

conditions, it is possible to use the body diodes of the power

MOSFETs to clamp the reverse voltage to approximately

4 V. In this case, the additional diode in the VBB connection

will prevent damage to the A4964 and the VBRG input will

survive the reverse voltage.

A4964

VBRG

VBB

PAD GND

GND

CSP

CSM

RSENSE

Motor

+Supply

Optional reverse

battery protection

Controller Supply Ground

Power Ground

Supply

Common

Figure 26: Supply Routing Suggestions

A4964 Datasheet(PDF) 82 Page - Allegro MicroSystems

A4964 Datasheet(HTML) 82 Page - Allegro MicroSystems

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