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A4964 Datasheet(PDF) 71 Page - Allegro MicroSystems |
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A4964 Datasheet(HTML) 71 Page - Allegro MicroSystems |
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71 / 92 page ![]() Sensorless Sinusoidal Drive BLDC Controller A4964 71 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Serial Register Reference 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 21: Speed loop 1 0 1 0 1 WR SGL4 SGL3 SGL2 SGL1 SGL0 SG3 SG2 SG1 SG0 P 0 0 1 0 1 0 1 0 1 22: Speed loop 1 0 1 1 0 WR DV1 DV0 DF1 DF0 SR2 SR1 SR0 P 0 1 0 0 0 0 0 0 0 23: Speed loop 1 0 1 1 1 WR SL3 SL2 SL1 SL0 SH3 SH2 SH1 SH0 P 0 0 1 1 1 0 1 1 1 Register 21: Speed Control Loop Configuration SGL[4:0] Speed Control Acceleration Limit KSL = 6.3 + (n × 6.4) Hz where n is a positive integer defined by SGL[4:0], e.g. when SGL[4:0] = [0 0111] then KSL = 51.5 Hz. The range of KSL is 6.3 Hz to 204.7 Hz. SG[3:0] Speed Control Gain KS = 1 + (n × 2) where n is a positive integer defined by SG[3:0], e.g., when SG[3:0] = [1000] then KS = 9. The range of KS is 1 to 31. Register 22: Speed Control Loop Configuration DV[1:0] Duty Cycle Compensation DV1 DV0 Nominal supply voltage Default 0 0 Disabled 0 1 12 V D 1 0 24 V 1 1 12 V DF[1:0] Deceleration Factor DF1 DF0 Deceleration factor Default 0 0 1 D 0 1 2 1 0 5 1 1 10 Register 22: Speed Control Loop Configuration (continued) SR[2:0] Speed Control Resolution SR2 SR1 SR0 Speed Resolution Default 0 0 0 0.1 Hz D 0 0 1 0.2 Hz 0 1 0 0.4 Hz 0 1 1 0.8 Hz 1 0 0 1.6 Hz 1 0 1 3.2 Hz 1 1 0 3.2 Hz 1 1 1 3.2 Hz Register 23: Speed Control Loop Configuration SL[3:0] Underspeed (Low-Speed) Threshold fSL = 8 × n × fRES (Hz) where n is a positive integer defined by SL[3:0], fSL is the underspeed threshold, and fRES is the speed resolution defined by SR[2:0]. SH[3:0] Underspeed (High-Speed) Threshold fSH = [127 + (n × 128)] × fRES (Hz) where n is a positive integer defined by SH[3:0], fSH is the underspeed threshold, and fRES is the speed resolution defined by SR[2:0]. |
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