A4964 datasheet(23/92 Pages) ALLEGRO

23 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LIN. LIN bus connection compliant with LIN 2.2 A. This input

can also be used as a PWM that can be passed to the LRX output

or used directly as the demand input when operating in stand-

alone mode.

LTX. LIN or FAULT transmit logic level input.

LRX. LIN or PWM receive logic level output.

IG. Ignition switch input, with resistor pull-down, to disable

or wake-up the A4964 and enable the logic regulator for the

microcontroller. When not used, IG should be tied to ground to

minimize the effect on the supply current in the sleep state.

DIAG. Programmable diagnostic output. Can be shorted to

ground or VBB without damage.

WDOG. Microcontroller watchdog logic input with resistor

pull-down. Window watchdog with programmable minimum and

maximum clock period.

MRSTn. Microcontroller reset control output. Holds the micro-

controller in reset until supplies are available. Resets the micro-

controller in case of watchdog failure.

SDI. Serial data input with resistor pull-down. 16-bit serial word

input msb first.

SDO. Serial data output. High impedance when STRn is high.

Outputs bit 15 of the Diagnostic register, the fault flag, as soon as

STRn goes low.

SCK. Serial clock input with resistor pull-down. Data is latched

in from SDI on the rising edge of CLK. There must be 16 rising

edges per write and SCK must be held high when STRn changes.

STRn. Serial data strobe and serial access enable input with

resistor pull-up. When STRn is high, any activity on SCK or SDI

is ignored and SDO is high impedance, allowing multiple SDI

slaves to have common SDI, SCK, and SDO connections.

Supplies and Regulators

MAIN POWER SUPPLY

A single power supply voltage is required. The main power sup-

ply, VBB, should be connected to VBB through a reverse voltage

protection circuit. A 100 nF ceramic decoupling capacitor must be

connected close to the supply and ground terminals of the A4964.

An internal regulator provides the supply to the internal logic. All

logic is guaranteed to operate correctly to below the VBB POR

level, ensuring that the A4964 will continue to operate safely

until all logic is reset when a power-on-reset state is present.

The A4964 will operate within specified parameters with VBB

from 5.5 to 50 V. Below 5.5 V, the gate drive outputs may be

inactive, but the A4964 will continue to respond through the

serial interface with a supply down to 3.5 V. It will remain in a

safe state between 0 and 50 V under all supply switching condi-

tions. This provides a very rugged solution for use in the harsh

automotive environment.

At power-up, the logic inputs and outputs will remain disabled

until VLR rises above the rising undervoltage threshold, VLRON. If

the WD mask bit is saved as 0 in non-volatile EEPROM (NWM),

the MRSTn output will remain low for 10 ms. If the WD mask

bit is saved as 1 in NWM, the MRSTn output will remain low for

10 ms or until the first valid serial transfer (whichever occurs first).

After the MRSTn output goes high, the gate drive outputs will be

re-enabled as described in the Fault Action section.

VLR REGULATOR

An integrated, programmable, linear regulator is provided to

supply the logic I/O and external logic-level circuits, such as a

microcontroller or interface circuit. The output of the regulator

on the VLR terminal is derived from VBB and can be selected as

3.3 or 5 V using the VLR bit. The logic I/O threshold levels are

also determined by the VLR bit, allowing the A4964 to match the

logic I/O levels of external logic.

The regulator includes current limit, undervoltage, and short pro-

tection. The current limiting circuit will reduce the output voltage

to ensure that the output current does not exceed the current limit,

ILROC. If the output voltage drops below the falling undervoltage

threshold, VLROFF, the MRSTn output will go low and can be

used to reset an external microcontroller.

If the output voltage falls below the regulator shutdown thresh-

old, VLROSD, for a period exceeding the shutdown lockout period,

tLRLO, the regulator is turned off and all logic inputs and outputs

are disabled. In this state a small pilot current, ILROP, is driven

through the regulator output to detect load resistance. If the resul-

tant voltage rises above the regulator enable threshold, VLROE,

the regulator immediately attempts to restart.

At power-up, or when the regulator restarts, full output current is

delivered for a period equal to the shutdown lockout period. Dur-

ing this time, the output voltage is not monitored for short-circuit

conditions in order to ensure reliable regulator startup.

A4964 Datasheet(PDF) 23 Page - Allegro MicroSystems

A4964 Datasheet(HTML) 23 Page - Allegro MicroSystems

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