A4964 datasheet(28/92 Pages) ALLEGRO

28 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

is usually used when the LIN terminal is used as a PWM input,

either in SPI mode or in standalone mode. If the LIN terminal

does not remain in the changed state for longer than the wake

time, tBUSWK, then the A4964 returns to the sleep state.

When a valid wake request is detected on the LIN terminal or

the IG terminal transitions from low to high, the A4964 will exit

normal the sleep state, turn on all regulators and control circuits,

and commence operation.

At this time, if the LEN bit is 0, the LIN interface will remain in

the standby state where the LIN terminal is a passive input. The

LRX output will indicate the state of the LIN terminal but the sig-

nal on the LTX terminal is ignored. The LIN interface becomes

fully active when LEN is set to 1. If the default value of LEN is

1, then the standby state is bypassed and the LIN interface is fully

active as soon as the internal regulators are fully active.

LIN

State

LEN

Sleep

Standby

Active

tBUSWK

tHDom

tHRec

Figure 13a: LIN Wake Sequence and Timing

State

LEN

Sleep

Standby

Active

LIN

(PWM)

tBUSWK

tHDom

tHRec

Figure 13b: PWM Wake Sequence and Timing

Motor Drive

The motor drive consists of three half-bridge gate drive outputs,

each driving one leg of an external three-phase MOSFET power

bridge. The state of the gate drive outputs is determined by a

three-phase PWM generator that determines the necessary PWM

duty cycle required at each of the three-phase connections to the

motor.

GATE DRIVE

The A4964 is designed to drive external, low on-resistance,

power n-channel MOSFETs. It will supply the large transient

currents necessary to quickly charge and discharge the external

MOSFET gate capacitance in order to reduce dissipation in the

external MOSFET during switching. The charge current for

the low-side drives and the recharge current for the bootstrap

capacitors is provided by the capacitor on the VREG terminal.

The charge current for the high-side drives is provided by the

bootstrap capacitors connected between the Cx and Sx terminal,

one for each phase. The MOSFET gate charge and discharge rate

can be controlled using an external resistor in series with the con-

nection to the gate of the MOSFET or by selecting the gate drive

current and timing using a group of parameters set via the serial

interface.

GATE DRIVE VOLTAGE REGULATION

The gate drivers are powered by a programmable voltage internal

regulator which limits the supply to the drivers and therefore

the maximum gate voltage. At low supply voltage, the regulated

supply is maintained by a charge pump boost converter which

requires a pump capacitor, typically 470 nF, connected between

the CP1 and CP2 terminals.

The regulated voltage, VREG, can be programmed to 8 or 11 V

and is available on the VREG terminal. The voltage level is

selected by the value of the VRG bit. When VRG = 1, the voltage

is set to 11 V; when VRG = 0, the voltage is set to 8 V. A suf-

ficiently large storage capacitor (see applications section) must

be connected to this terminal to provide the transient charging

current to the low side drivers and the bootstrap capacitors.

LOW-SIDE GATE DRIVE

The low-side, gate-drive outputs on GLA, GLB, and GLC are

referenced to the GND terminal. These outputs are designed

to drive external N-channel power MOSFETs. GLx = ON (or

“high”) means that the upper half of the driver is turned on and it

will source current to the gate of the low-side external MOSFET,

turning it on. GLx = OFF (or “low”) means that the lower half of

A4964 Datasheet(PDF) 28 Page - Allegro MicroSystems

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