A4964 datasheet(49/92 Pages) ALLEGRO

49 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

disabled. This fault state will be latched until the next PWM-on

state for the associated phase. In some cases, this will allow the

A4964 to continue to operate the motor in a reduced functional

mode depending on the specific fault condition.

When a loss of synchronization is detected, all the gate drive

outputs are disabled and the motor coasts. If the restart bit, RSC,

is set to 1, the A4964 immediately goes into a startup sequence.

If RSC = 0, the loss of synchronization fault state is latched and

all gate drive outputs remain disabled until a demand input reset,

a RUN bit reset, a serial read of the Status register with DSR = 0,

or a power-on-reset occurs.

In all cases, any fault bits that have been set in the diagnostic

registers are latched and only reset when a power-on-reset state is

present or when the associated fault bit is read through the serial

interface with DSR = 0.

FAULT MASKS

Individual diagnostics, except POR and system error, can be dis-

abled by setting the corresponding bit in the mask register. If a bit

is set to one in the mask register, then the corresponding diagnos-

tic will be completely disabled. No fault states for the disabled

diagnostic will be generated, no fault flags or diagnostic bits will

be set, and no fault actions will be taken. See the mask register

definition for bit allocation.

Care must be taken when diagnostics are disabled to avoid poten-

tially damaging conditions.

CHIP-LEVEL DIAGNOSTICS

Parameters, which are critical for safe operation of the A4964

and the external MOSFETs, are monitored. These include serial

interface, chip temperature, minimum internal logic supply volt-

age, and the minimum motor supply voltage. Faults are latched in

the Status or Diagnostic register when they occur and the register

is only reset by a Status or Diagnostic register reset.

CHIP FAULT STATE: POWER-ON RESET

The supply to the logic sections of the A4964 is generated by an

internal regulator from VBB and is monitored to ensure correct

logical operation. The internal logic is guaranteed to operate with

the voltage at the VBB terminal, VBB, down to VBBR. When VBB

drops below the VBBR threshold, then the logical function of the

A4964 cannot be guaranteed, all outputs will be immediately dis-

abled and all the logic reset. The A4964 will enter a power-down

state and all internal activity, other than the logic supply voltage

monitor will be suspended.

When VBB rises above the VBBR threshold, the A4964 will exit

the power down state, all serial control registers will be reset to

their power-on state, and all fault states will be reset. The FF bit

and the POR bit in the Status register will be set to one to indicate

that a power-on-reset has taken place. In general, the VSU, VRU,

and VLU bits may also be set following a power-on-reset as the

regulators may not have reached their respective rising undervolt-

age thresholds until after the register reset is completed.

At power-up, the logic inputs and outputs will remain disabled

until VLR rises above the rising undervoltage threshold, VLRON. If

the WD mask bit is saved as 0 in non-volatile EEPROM (NWM),

the MRSTn output will remain low for 10 ms. If the WD mask

bit is saved as 1 in NWM, the MRSTn output will remain low for

10 ms or until the first valid serial transfer (whichever occurs first).

After the MRSTn output goes high, the gate drive outputs will be

re-enabled as described in the Fault Action section.

The same power-on-reset sequence occurs for initial power-on

or for a VBB “brown-out” where VBB only drops below VBBR

momentarily.

CHIP FAULT STATE: OVERTEMPERATURE

Two temperature thresholds are provided. A hot warning and an

overtemperature shutdown.

• If the chip temperature rises above the temperature warning

threshold, TJW, the thermal warning bit, TW, will be set in

the Status register. No action will be taken by the A4964

when a thermal warning fault condition is present. When the

temperature drops below TJW by more than the hysteresis value,

TJWHys, the fault condition is removed. The thermal warning bit,

TW, remains latched in the Status register until reset.

• If the chip temperature rises above the over temperature

threshold, TJF, the over temperature bit, OT, will be set in the

Status register.

If ESF = 1, all gate drive outputs will be disabled, the VLR

regulator is shut down and MRSTn will go low. All A4964 func-

tions other than the regulator remain active. When TJ drops by

more than the overtemperature threshold (TJ < TJF – TJHyst), the

regulator will remain shut down and MRSTn will remain low for

10 ms. After this timeout, MRSTn goes high and the regulator is

re-enabled and attempts to restart. The overtemperature bit, OT,

remains latched in the Status register until reset.

If ESF = 0, no circuitry will be disabled and action must be taken

by the user to limit the power dissipation in some way so as to

prevent overtemperature damage to the chip and unpredictable

device operation. When the temperature drops below TJF by more

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