A4964 datasheet(46/92 Pages) ALLEGRO

46 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Diagnostics

Multiple diagnostic features provide fault monitoring for the

basic chip status, for the state of the external bridge and for the

motor control function. Most of the non-critical diagnostics can

be masked by setting the appropriate bit in the mask register. The

detectable faults are listed in table 5.The fault status is available

through the serial interface or through the DIAG output. The

serial output, SDO, can also be programmed to provide a divided

version of the system clock that can be used for clock frequency

verification or system calibration.

SERIAL STATUS REGISTER

The serial interface allows detailed diagnostic information to be

read from the Status register at any time.

The first bit (bit 15) of the Status register contains a common

fault flag, FF, which will be high if any of the fault bits in the

registers have been set. This allows fault condition to be detected

using the serial interface by simply taking STRn low. As soon as

STRn goes low, the first bit in the Status register can be read to

determine if a fault has been detected at any time since the last

Status or Diagnostic register reset. In all cases, the fault bits in the

diagnostic registers are latched and only cleared after the associ-

ated fault bit is read through the serial interface with DSR = 0.

DIAGNOSTIC REGISTER

The diagnostic register provides additional details of any VDS

overvoltage or bootstrap undervoltage faults. It also provides an

indication when the reported motor speed is above the maximum

programmable level.

The status and diagnostic registers are described further in the

serial interface section description below.

DIAG OUTPUT

DIAG is a battery-compliant open-drain pull-down output that

provides the following four optional signals selected by the

DGS[1:0] variable:

DGS = 0: An active-low fault flag which will be low when a

fault is present or a fault state is latched.

DGS = 1: An FG speed signal providing a square wave at the

electrical cycle frequency.

DGS = 2: Time-based pulses to differentiate the fault groups

as described in table 5 below. DIAG will be inactive when no

fault is present.

DGS = 3: Time-based pulses to differentiate the fault groups

as described in table 5 below. DIAG will output the FG signal

when no fault is present.

When operating in stand-alone mode and DGS = 0 or 2, DIAG

can be externally connected directly to the LIN terminal or to the

LTX input to superimpose the fault information onto the PWM

input. When DGS = 2, the PWM input duty cycle detection will

ignore the state of the PWM signal when DIAG is low and main-

tain the last detected demand input.

Further details on using the DIAG output for error reporting are

provided in the applications section in this datasheet.

Table 4: DIAG Pulse Definition and Fault Allocation

DGS[1:0]

Fault Description

Fault Group

DIAG Output

Priority

No Fault

–

Serial Error

VBB POR

Temperature Warning

System Error

System

VBB Undervoltage

Undervoltage

L: 2.5 s / H: 1 s

VLR Undervoltage

VREG Undervoltage

Bootstrap Undervoltage

Over Temperature

Temperature

L: 2 s / H: 1 s

VDS Overvoltage

Short Detect

L: 1 s / H: 1 s

Loss of Synchronization

Motor lock

L: 1.5 s / H: 1 s

A4964 Datasheet(PDF) 46 Page - Allegro MicroSystems

A4964 Datasheet(HTML) 46 Page - Allegro MicroSystems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL