GD25Q257DFJR datasheet(27/99 Pages) GIGADEVICE

27 / 99 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q257D

8.6. Read Extended Register (C8H)

Extended Register contains ECC Status Bits, several device configuration bits, and Address Bit A24. The Read

Extended Register instruction is entered by driving CS# low and sh

ifting the instruction code “C8H” into the SI pin on the

rising edge of SCLK. The Extended Register bits are then shifted out on the SO pin at the falling edge of SCLK with most

significant bit (MSB) first as shown in Figure 10.

When the device is in the 4-Byte Address Mode, the value of A24 Bit is not ignored.

Figure 10 Read Extended Register Sequence Diagram

8.7. Write Extended Register (C5H or 56H)

The Write Extended Register command could be executed no matter the Write Enable Latch (WEL) bit is 0 or 1. The

Write Extended Register

instruction is entered by driving CS# low, sending the instruction code “C5/56H”, and then writing

the Extended Register data Byte as illustrated in Figure 11.

C5H is used to write A24 bit in the Extended Register. 56H is used to write EA5-EA2 (DLP, ECS bits).

Upon power up or the execution of a Software/Hardware Reset, the Extended Register bit values will be cleared to 0.

Figure 11 Write Extended Register Sequence Diagram

Command

C8H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Extended Addr.

MSB

Extended Addr.

Command

C5/56H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Extended Addr.

GD25Q257DFJR Datasheet(PDF) 27 Page - GigaDevice Semiconductor (Beijing) Inc.