GD25Q257DFJR datasheet(10/99 Pages) GIGADEVICE

10 / 99 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q257D

status register, programming, or erasing in progress.

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being

low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge

of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).

The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD

operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and

then CS# must be at low.

Figure 3 HOLD Condition

RESET Function

The RESET# pin allows the device to be reset by the control. The HOLD#/RESET#(IO3) pin can be configured as a

RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. For Special Order of the SOP16

and TFBGA packages, a dedicated RESET# pin is provided and it is independent of QE bit setting.

The RESET# pin goes low for a minimum period of tRLRH

(1 μs) will reset the flash. After reset cycle, the flash is at

the following states:

-Standby mode

-All the volatile bits will return to the default status as power on.

Figure 4 RESET Condition

HOLD

CS#

SCLK

HOLD#

CS#

RESET#

RESET

GD25Q257DFJR Datasheet(PDF) 10 Page - GigaDevice Semiconductor (Beijing) Inc.