GD25Q257DFJR datasheet(70/99 Pages) GIGADEVICE

70 / 99 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q257D

8.38.

Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its

default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch

status (WEL), Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).

The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command

sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending

Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately

tRST /tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going

or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is

recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.

Figure 80. Enable Reset and Reset command Sequence Diagram

Note: Enable Reset (66H) and Reset (99H) commands have is of no effect when the device is in Quad I/O DTR Continuous

Read Mode. The only way to quit the Quad I/O DTR Continuous Read Mode is to set

the “Continuous Read Mode” bits (M5-

4) not equal to (1,0).

Command

66H

CS#

SCLK

High-Z

Command

99H

GD25Q257DFJR Datasheet(PDF) 70 Page - GigaDevice Semiconductor (Beijing) Inc.