GD25Q257DFJR datasheet(14/99 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q257D

Erase command is accepted.

TB bit

The Top Bottom (TB) bit is non-volatile (OTP). The Top/Bottom (TB) bit is used to configure the Block Protect area by

BP bit (BP3, BP2, BP1, and BP0), starting from Top or Bottom of the memory array. The TB bit

is defaulted as “0”, which

means Top area protect. When it

is set to “1”, the protect area will change to Bottom area of the memory device. This bit is

written with the Write Status Register (WRSR) command.

BP3, BP2, BP1, BP0 bits

The Block Protect (BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.

When the Block Protect (BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protected against

Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP3, BP2, BP1, and BP0)

bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed

only if none sector or block is protected.

SRP bit

The Status Register Protect (SRP) bit is a non-volatile Read/Write bit in the status register. The SRP bit controls the

method of the write protection: software protected, hardware protected, or hardware unprotected.

Table 9. Status Register Protect (SRP) bit

SRP

WP#

Status Register

Description

Software Protected

The Status Register can be written to after a Write Enable command,

WEL=1.(Default)

Hardware Protected

WP#=0, the Status Register locked and cannot be written to.

Hardware Unprotected

WP#=1, the Status Register is unlocked and can be written to after a

Write Enable command, WEL=1

QE bit

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When

the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad

IO2 and IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly

to the power supply or ground.)

LB3, LB2, LB1 bits.

The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S11, S12, S13) that provide

the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are

unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

ECC Enable bit

The on chip ECC engine can be enabled or disabled by the ECC bit. When ECC=1, ECC function is

enabled for all Program and Read operations to ensure data integrity and improve device reliability. Aligned 8-

Byte granularity is required for Program operations, but not for Read operations.

SUS1, SUS2 bits

The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an

Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset

(66H+99H) command as well as a power-down, power-up cycle.

GD25Q257DFJR Datasheet(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc.

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