GD25Q257DFJR datasheet(43/99 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q257D

8.15.

Quad I/O DTR Read (EEH or EDH)

The DTRQIO instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad

Enable (QE) bit of status Register must be set to "1" before sending the DTRQIO instruction. The address (interleave on 4

I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both rising and

falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which

means four bits at rising edge of clock, the other four bits at falling edge of clock. The first address Byte can be at any

location. The address is automatically increased to the next higher address after each Byte data is shifted out, so the whole

memory can be read out at a single DTRQIO instruction. The address counter rolls over to 0 when the highest address has

been reached. Once writing DTRQIO instruction, the following address/dummy/data out will perform as 8-bit instead of

previous 1-bit.

While Program/Erase/Write Status Register cycle is in progress, DTRQIO instruction is rejected without any impact on

the Program/Erase/Write Status Register current cycle.

Quad I/O DTR

Read with “Continuous Read Mode”

The Quad I/O DTR

Read command can further reduce command overhead through setting the “Continuous Read

Mode” bits (M7-0) after the input address. If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O DTR

Read command (after CS# is raised and then lowered) does not require the EDH/EEH

command code. If the “Continuous

Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EDH/EEH command code, thus returning

to normal operation. The only way to quit the Quad I/O DTR Continuous Read

Mode” is to set the “Continuous Read Mode”

bits (M5-4) not equal to (1,0).

Figure 37. DTR Quad I/O Fast Read Sequence Diagram (ADS=0)

Command

EDH

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11

18 19

4 0 4 0 4 0 4 0

4 0 4 0

5 1 5 1 5 1 5 1

5 1 5 1

A23-0

6 2 6 2 6 2 6 2

6 2 6 2

7 3 7 3 7 3 7 3

7 3 7 3

IO2

Configurable

Dummy

Byt e1

Byt e2

M7-0

1 0 1

DQS

IO3

GD25Q257DFJR Datasheet(PDF) 43 Page - GigaDevice Semiconductor (Beijing) Inc.

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