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AFD4400 Datasheet(PDF) 44 Page - NXP Semiconductors |
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AFD4400 Datasheet(HTML) 44 Page - NXP Semiconductors |
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44 / 101 page ![]() AFD4400 Digital Front End Processor Data Sheet, Rev. 0 Electrical characteristics Freescale Semiconductor 44 3.2 Power sequencing The following figure depicts the power-up sequencing requirements.There is no timing parameters associated with it; board designers need to ensure the sequence. Figure 4. Power-up sequencing 3.2.1 Power-on ramp rate This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry. Table 19 provides the power supply ramp rate specifications. Table 19. Power supply ramp rate Parameter Min Max Unit Note Required ramp rate for all voltage supplies — 25 V/mS 3,4 Required ramp rate for P1OVDD and P2OVDD — 25 V/mS 1, 2,3,4 Note: 1. P1OVDD should be tied to ground during functional applications.This supply is needed in the factory for programming of memory repair fuses. 2. P2OVDD should be tied to ground during functional applications. It can be driven to the specified supply during functional fuse programming. 3. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. 4. Over full recommended operating temperature range (see Table 3). RSTIN_B VDD TRST_B P1OVDD/P2OVDD Note : 1. The Core VDD should come first. Other supplies can be in any order once the core supply is up and stable. 2. RSTIN_B and TRST_B should remain asserted till the power supplies get stable. 3. Refer to DC operating condition for supply specification. FVDD/JVDD/GVDD1-9/MVDD/TVDD/ MVDD1_8/TVDD1_8/LVDD1-3/ SD1-3_XPA_DVDD 4. During power off VDD should be the last supply to get turned off. |
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