AFD4400 datasheet(64/101 Pages) NXP

64 / 101 page

AFD4400 Digital Front End Processor Data Sheet, Rev. 0

Electrical characteristics

Freescale Semiconductor

This figure shows the RMII receive AC timing diagram.

Figure 19. RMII receive AC timing diagram

3.6.5.4

MII management AC timing specifications

This table provides the MII management AC timing specifications.

Table 41. MII management AC timing specifications

At recommended operating conditions with VDDGPIO = 3.3 V ± 5%.

Parameter

Symbol1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

——

2.5

MHz

MDC period

tMDC

400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO delay

tMDKHDX

× taxi) – 3

—

× taxi) + 3

2, 3

MDIO to MDC setup time

tMDDVKH

—

MDIO to MDC hold time

tMDDXKH

0—

—

Notes:

1. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency

of the MgmtClk Clock MDC).

2. This parameter is dependent on the platform (AXI) clock frequency (faxi). The delay is equal to 8 platform clock periods

±3 ns. For example, with a platform clock of 307.2 MHz, the min/max delay is 26 ns ± 3 ns.

3. taxi is the platform AXI bus clock.

TSEC1_TX_CLK

TSEC1_RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

TSEC1_CRS_DV

TSEC1_RX_ER

tRMRDV

Valid Data

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