AFD4400 datasheet(62/101 Pages) NXP

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AFD4400 Digital Front End Processor Data Sheet, Rev. 0

Electrical characteristics

Freescale Semiconductor

This figure shows the RGMII AC timing and multiplexing diagrams.

Figure 17. RGMII timing and multiplexing diagrams

Clock period duration

tRGT

7.2

8.0

8.8

Duty cycle for 10BASE-T and 100BASE-TX

tRGTH/tRGT

3,4

Duty cycle for Gigabit

tRGTH/tRGT

—

Note:

2. This implies that the PC board design requires clocks to be routed such that an additional trace delay greater than 1.5 ns

is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip. If

so, additional PCB delay is probably not needed.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed

transitioned between.

5. The frequency of TSEC1_RX_CLK (input) should not exceed the frequency of TSEC1_GTX_CLK (output) by more than

300 ppm.

Table 38. RGMII AC timing specifications (continued)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

TSEC1_GTX_CLK

tRGT

tRGTH

tSKRGT_TX

TSEC1_TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At MAC, output)

TSEC1_TXD[8:5][3:0]

TSEC1_TXD[7:4][3:0]

TSEC1_TX_CLK

(At PHY, input)

TSEC1_RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

TSEC1_RX_CLK

(At MAC, input)

tSKRGT_RX

tRGTH

tRGT

TSEC1_RX_CLK

(At PHY, output)

TSEC1_RXD[8:5][3:0]

TSEC1_RXD[7:4][3:0]

tSKRGT_RX

PHY equivalent to tSKRGT_TX

tSKRGT_TX

PHY equivalent to tSKRGT_RX

(At MAC, output)

(At PHY, output)

PHY equivalent to tSKRGT_TX

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