AFD4400 datasheet(63/101 Pages) NXP

63 / 101 page

Electrical characteristics

AFD4400 Digital Front End Processor Data Sheet, Rev. 0

Freescale Semiconductor

WARNING

Freescale guarantees timings generated from the MAC. Board designers must ensure

delays needed at the PHY or the MAC.

3.6.5.3

RMII AC timing specifications

In RMII mode, the reference clock should be fed to TSEC1_TX_CLK. This section describes the RMII transmit and receive

AC timing specifications.

This table lists the RMII transmit AC timing specifications.

This figure shows the RMII transmit AC timing diagram.

Figure 18. RMII transmit AC timing diagram

This table lists the RMII receive AC timing specifications.

Table 39. RMII transmit AC timing specifications

Parameter

Symbol

Min

Typ

Max

Unit

Typ

TSEC1_TX_CLK clock period

tRMT

—20.0

—

TSEC1_TX_CLK duty cycle

tRMTH

—

TSEC1_TX_CLK peak-to-peak jitter

tRMTJ

——250

—

TSEC1_TX_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX

2.0

—

10.0

—

Table 40. RMII receive AC timing specifications

Parameter

Symbol

Min

Typ

Max

Unit

Note

TSEC1_TX_CLK clock period

tRMR

—

20.0

—

TSEC1_TX_CLK duty cycle

tRMRH

—

TSEC1_TX_CLK peak-to-peak jitter

tRMRJ

——

250

—

RXD[1:0], CRS_DV, RX_ER set-up time to TSEC1_TX_CLK

rising edge

tRMRDV

4.0

—

RXD[1:0], CRS_DV, RX_ER hold time to TSEC1_TX_CLK

rising edge

tRMRDX

2.0

—

TSEC1_TX_CLK

TSEC1_TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TSEC1_TX_EN

TSEC1_TX_ER

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