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AFD4400 Datasheet(PDF) 1 Page - NXP Semiconductors |
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AFD4400 Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 101 page  Freescale Semiconductor Data Sheet: Technical Data © 2015 Freescale Semiconductor, Inc. All rights reserved. The following list provides an overview of the feature set: • Flexible radio configurations – Up to eight carriers in single or multi-mode combinations – LTE(FDD and TDD), WCDMA, N-CDMA, and GSM supported – Supported at least 80 MHz total carrier bandwidth – Supported at least 100 MHz of instantaneous bandwidth with non-contiguous carriers. – Up to eight transmitters, eight receivers, and four observability/sampling receivers – Ability to cascade to support multi-sector or distributed antenna systems • Fully programmable signal processing paths – Transmit path: eight vector signal processors – Receive path: two vector signal processors – Observability Path: one vector signal processor – Processor elements sized to support common RF subsystem processing requirements—crest factor reduction, digital pre-distortion (DPD), channel filters, up and down conversion, carrier combining and separation, IQ compensation equalization, interpolation and decimation, and beam forming – Transmit/receive processing, busing, and memory system sized for—closed-loop DPD operation up to 491.52 Msps, maximum transmit sample rate of 491.52 Msps, maximum receive sample rate of 245.76 Msps, and maximum observability/sampling rate of 491.52 Msps • Industry standard interfaces to external components – CPRI v4.2 modem interface – JESD204B transceiver interface – Ethernet OA&M interface – AISG antenna accessory interface •ARM® Cortex®-A9 processor – 32 KB L1 instruction cache – 32 KB L1 data cache – 256 KB L2 cache – Neon extension for SIMD and floating point instructions • Hierarchical memory architecture – Local memories within each vector signal processor domain – System level shared memory – 32-bit DDR3 interface with 500 MHz memory bus speed. – External NOR and SPI flash • Debug – Built around ARM® CoreSight™ architecture – JTAG run control interface – 32-bit instruction trace port – Dedicated JESD204B interface for debug IQ streaming • Low-power design techniques – Clock gating and isolation of clocks – Power gating (PG) – Power islands AFD4400 Digital Front End Processor Data Sheet Document Number: AFD4400 Rev. 0, 10/2015 AFD4400 FC PBGA 1152 35 mm x 35 mm |
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