AFD4400 datasheet(45/101 Pages) NXP

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Electrical characteristics

AFD4400 Digital Front End Processor Data Sheet, Rev. 0

Freescale Semiconductor

3.3

RESET initialization

This section describes the electrical specifications for the RESET initialization timing requirements.

The figure below shows reset timing diagram.

Figure 5. Reset timing diagram

NOTE

As shown in Figure 5, a stable DEVCLK1_P/N is required (at least one DEVCLK period

before) to AFD4400 before releasing the RSTIN_B pin.

This table provides RESET initialization timing specifications.

Table 20. Reset initialization timing specifications

Parameter

Symbol

Min

Max

Unit

Note

CC1

Duration of RSTIN_B to be qualified as valid (assumption:

Input slope = 5 ns)

TRSTINV

—

CC2

Duration of RSTOUT_B, RSTOUTn_B assertion after

de-assertion of RSTIN_B

TRSTOUTW

200

—

μs2

CC3

Delay from RSTIN_B to RSTOUT_B, RSTOUTn_B assertion TROUTLRINV

—35

CC4

Duration of RSTOUTn_B for software bit based assertion

TRSTOUTnW

—

μs1,2

Note:

1. RSTOUT1_B to RSTOUT7_B can be asserted by writing into corresponding register bits in System Reset Controller

module. Refer AFD4400 Reference Manual for details.

2. RSTOUT1_B to RSTOUT7_B pulse width matches RSTOUT_B timing in case of power on reset, cold reset and warm

reset assertion.

RSTOUT_B

CC3

CC2

CC1

RSTIN_B

50%

DEVCLK1_P/N

Stable clock

RSTOUTn_B

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