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AFD4400 Datasheet(PDF) 71 Page - NXP Semiconductors

Part # AFD4400
Description  AFD4400 Digital Front End Processor Data Sheet
PDF  101 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

AFD4400 Datasheet(HTML) 71 Page - NXP Semiconductors

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Electrical characteristics
AFD4400 Digital Front End Processor Data Sheet, Rev. 0
Freescale Semiconductor
71
The figure below depicts Quad-SPI timing.
Figure 29. Quad-SPI input timing
3.6.11
SerDes
The following subsections define the AC-level specifications for the CPRI, SGMII and JESD204B data lines.
3.6.11.1
Signal terms definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines the terms that are used in
the description and specification of differential signals.
Hold time requirement for incoming data
TQSDXKL
1.0
——ns
—
Note:
1. All data are based on a negative edge data launch from AFD4400 and a negative edge data capture as shown in the
timing diagrams.
2. Timings correspond to QSPI_SMPR = 0x0000_000x.
3. A negative value of hold is an indication of pad delay on the clock pad (delay between the edge capturing data inside
device and the edge appearing at the pin).
4. 15 pF load has been assumed on the pads.
Table 47. Quad-SPI module timing characteristics (continued)
Parameter
Symbol
Value
Unit
Note
Min
Typ
Max
QSPI_CK
QSPI_IO[3:0]
TQSKLDV
1. Last address out
2. Address captured at flash
3. Data out from Flash
4. This is SPI protocol defined Ideal Data Capture edge.The capture edge can be programmed as shown in 5,6,7,8.
5. Delayed data captured edge with QSPI_SMPR=0000_000x
6. Delayed data captured edge with QSPI_SMPR=0000_002x
7. Delayed data captured edge with QSPI_SMPR=0000_004x
8. Delayed data captured edge with QSPI_SMPR=0000_006x
QSPI_IO[3:0]
1
2
3
4
5
6
(For Output)
(For Input)
TQSDVKL
TQSDXKL
7
8



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