AFD4400 datasheet(47/101 Pages) NXP

47 / 101 page

Electrical characteristics

AFD4400 Digital Front End Processor Data Sheet, Rev. 0

Freescale Semiconductor

Half run mode

• Six VSPA running FIR with 100% utilization.

Remaining five power gated.

• ARM running code with 100% utilization.

• ARM Data accesses from DDR memory

• 4 JESD TX and 4 JESD RX at 9.8G rate, 1 lane

per interface

• 2 JESD RX for SRx function at 9.8G rate

• 2 CPRI running at 9.8G, one link in RE mode,

one link in REC mode

• Single Ethernet lane running at 1.25G

Maximum

105

VID

19.1

21.9

1,3,4

• Six VSPA running FIR 70% with 10% control

code. Remaining five power gated.

• ARM running code with 75% utilization

• 4 JESD TX and 4 JESD RX at 9.8G rate, 1 lane

per interface

• 2 JESD RX for SRx function at 9.8G rate

• 2 CPRI running at 9.8G, one link in RE mode,

one link in REC mode

Thermal

105

VID

15.3

18.1

2,3,4

Typical

VID

12.9

15.7

2,3,4,5

4T4R 40 MHz

bandwidth

• 4 Tx Antenna (153.6 MSPS)

• 4 Rx Antenna (76.8 MSPS)

• 2 SRx (153.6 MSPS)

• 40 MHz Occupied Bandwidth

• (8 - 5MHz LTE carriers per antenna)

• 40 MHz Instantaneous Bandwidth

• 153.6 MHz DPD Bandwidth

• 2 CPRI links at 9.8304Gbps rate

Thermal

105

VID

16.2

18.2

Full Standby

(CPRI active,

antenna paths

configured but

not active)

• All VSPA in partial powerdown waiting for go

event. Clocks enabled but gated.

• ARM in stop mode. Clocks enabled but gated.

Servicing only CPRI C&M messages

• 8 JESD TX and 8 JESD RX at 9.8G rate, 1 lane

per interface. Links active but no data transfer

(zeros sent, receive data ignored)

• 2 JESD RX for SRx function at 9.8G rate. Link

active but receive data ignored.

• 4 CPRI running at 9.8G, 2 links in RE mode, 2

links in REC mode

Typical

VID

3.4

7.2

Table 22. Power numbers (continued)

Characteristic

Condition

AFD4400 Datasheet(PDF) 47 Page - NXP Semiconductors

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