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AFD4400 Datasheet(PDF) 76 Page - NXP Semiconductors |
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AFD4400 Datasheet(HTML) 76 Page - NXP Semiconductors |
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76 / 101 page  AFD4400 Digital Front End Processor Data Sheet, Rev. 0 Electrical characteristics Freescale Semiconductor 76 This table lists the AC requirements for SerDes reference clock DEVCLKn_P/DEVCLKn_N. SGMII_REFCLK_P/SGMIIREFCLK_N total reference clock jitter at 10-6 BER (peak-to-peak jitter at refClk input) tCLK_TJ —— 86 ps — SGMII_REFCLK_P/SGMIIREFCLK_N rising/falling edge rate tCLKRR/tCLKFR 1— 4 V/ns 2 Differential input high voltage VIH VCM+200 mV —— mV 3 Differential input low voltage VIL —— VCM –200 mV mV 3 Rising edge rate (SGMII_REFCLK_P) to falling edge rate (SGMII_REFCLK_N) matching Rise-Fall Matching —— 20 % 4, 5 Notes: 1. Caution: Only 125 have been tested. In-between values do not work correctly with the rest of the system. 2. Measured from –200 mV to +200 mV on the differential waveform (derived from SGMII_REFCLK_P minus SGMII_REFCLK_N). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 35. 3. Measurement taken from differential waveform 4. Measurement taken from single-ended waveform 5. Matching applies to rising edge for SGMII_REFCLK_P and falling edge rate for SGMII_REFCLK_N. It is measured using a 200 mV window centered on the median cross point where SGMII_REFCLK_P rising meets SGMII_REFCLK_N falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SGMII_REFCLK_P must be compared to the fall edge rate of SGMII_REFCLK_N, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 36. Table 49. DEVCLKn_P/DEVCLKn_N input clock requirements Parameter Symbol Min Typ Max Unit Notes Frequency range tCLK_REF —122.88 — MHz 1 Clock frequency tolerance tCLK_TOL –100 — 100 ppm — Reference clock duty cycle (measured at 1.6 V) tCLK_DUTY 45 50 55 % — Single side band noise at 1 KHz tSSN_1K —— –85 dBC/Hz — Single side band noise at 10 KHz tSSN_10K — — –108 dBC/Hz — Single side band noise at 100 KHz tSSN_100K — — –128 dBC/Hz — Single side band noise at 1 MHz tSSN_1M — — –138 dBC/Hz — Single side band noise at 10 MHz tSSN_10M — — –138 dBC/Hz — Random jitter (1.2 MHz to 15 MHz) tJ_RANDOM —— 0.8 ps — Table 48. SGMII_REFCLK_P/SGMIIREFCLK_N (continued)requirement Parameter Symbol Min Typ Max Unit Notes |
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