AFD4400 datasheet(92/101 Pages) NXP

92 / 101 page

AFD4400 Digital Front End Processor Data Sheet, Rev. 0

Hardware design considerations

Freescale Semiconductor

NOTE

A higher capacitance value for C2 may be used to improve the filter as long as the other C2

parameters do not change (0402 body, X5R, ESL

≤ 0.5 nH).

Voltage for APVDD is defined at the input of the PLL supply filter and not the pin of

APVDD.

Figure 48. PLL power supply filter circuit

The SDx_AVDD_PLLn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal

clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 49. For maximum

effectiveness, the filter circuit is placed as closely as possible to the SDx_AVDD_PLLn balls to ensure it filters out as much

noise as possible. Prior to release of PLL reset, and start of PLL lock, the PLL supply must be at a stable and quiescent value.

The ground connection should be near the SDx_AVSS_PLLn balls. The 0.003-µF capacitors closest to the balls, followed by a

4.7-µF and 47-µF capacitor, and finally the 0.33

Ω resistor to the board supply plane. The capacitors are connected from

SDx_AVDD_PLLn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All

traces should be kept short, wide, and direct.

Figure 49. SerDes PLL power supply filter circuit

Note the following:

•SDx_AVDD_PLLn should be a filtered version of VDDSDIO.

•

Signals on the SerDes interface are fed from the VDDSDIO power plane.

•

Voltage for SDx_AVDD_PLLn is defined at the PLL supply filter and not the pin of SDx_AVDD_PLLn.

•

A 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitor are recommended. The size and material type

are important. A 0.33-

Ω ± 1% resistor is recommended.

•

There needs to be dedicated analog ground, SDx_AVSS_PLLn for each SDx_AVDD_PLLn pin up to the physical local

of the filters themselves.

•

The noise level on the SerDes PLL power supplies must be less than 10 mV Pk-Pk.

4.2.4

SerDes transceiver core supply filtering

VDDSDX should be supplied by a dedicated linear regulator. Systems may design to allow flexibility to address system noise

dependencies.

NOTE

For initial system bring-up, the linear regulator option is highly recommended.

APVDDn

GND

Low-ESL surface-mount capacitors

1.8 V source

4.7 µ

0.003 µ

0.33

47 µ

SDx_AVSS_PLLn

VDDSDIO

SDx_AVDD_PLLn

0 ohm(0603 sized) default resistance

VDDSDIO

Board Gnd

with provision to be changed to inductance

AFD4400 Datasheet(PDF) 92 Page - NXP Semiconductors

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