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AFD4400 Datasheet(PDF) 57 Page - NXP Semiconductors |
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AFD4400 Datasheet(HTML) 57 Page - NXP Semiconductors |
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57 / 101 page  Electrical characteristics AFD4400 Digital Front End Processor Data Sheet, Rev. 0 Freescale Semiconductor 57 3.6.3 DDR controller This table provides the timing parameters for DDR3 controller. This table provides the write timing parameters for DDR3 write cycle. This table provides the timing parameters for DDR3 read cycle. Table 32. DDR3 timing parameter ID Parameter Symbol Min Max Unit Note DDR0 Clock Period TMMKW 2— ns — DDR1 CK clock high-level width TMMKH 0.47 0.53 TMMKW — DDR2 CK clock low-level width TMMKL 0.47 0.53 TMMKW — DDR4 CS, RAS, CAS, CKE, WE, ODT setup time TMMKHOV 440 — ps — DDR5 CS, RAS, CAS, CKE, WE, ODT hold time TMMKHOX 315 — ps — DDR6 Address output setup time TMMKHOV2 440 — ps — DDR7 Address output hold time TMMKHOX2 315 — ps — Note: 1. All measurements are in reference to Vref level. 2. Measurements are done using balanced load and 25 Ω resistor from outputs to VDD_REF. Table 33. DDR3 write cycle ID Parameter Symbol Min Max Unit Note DDR17 DQ and DQM setup time to DQS (differential strobe) TMMDHDV 215 — ps — DDR18 DQ and DQM hold time to DQS (differential strobe) TMMDHDX 215 — ps — DDR21 DQS latching rising transitions to associated clock edges TMMKHDH –0.25 +0.25 TMMKW — DDR22 DQS high level width TMMDQSH 0.45 0.55 TMMKW — DDR23 DQS low level width TMMDQSL 0.45 0.55 TMMKW — Note: 1. To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window. 2. All measurements are in reference to Vref level. 3. Measurements are done using balanced load and 25 Ω resistor from outputs to VDD_REF. Table 34. DDR3 read cycle ID Parameters Symbol Min Max Unit Note DDR27 Tolerated skew for DDR_DQS - DDR_DQ TMMDSKEW -150 150 ps — Note: 1. To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle of DQ window. 2. All measurements are in reference to Vref level. 3. Measurements are done using balanced load and 25 Ω resistor from outputs to VDD_REF. |
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