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Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Figure 16 SXGA Frame Timing
Figure 17 VGA Frame Timing
The specifications shown in Table 9 apply for DVDD = +2.5V, DOVDD = +3.3V, TA = 25°C, sensor working at 15 fps,
external loading = 30 pF.
Table 9
Pixel Timing Specification
Symbol
Parameter
Min
Typ
Max
Unit
tp
PCLK period
20.83
ns
tpr
PCLK rising time
10
ns
tpf
PCLK falling time
5
ns
tdphr
PCLK negative edge to HREF rising edge
0
5
ns
tdphf
PCLK negative edge to HREF negative edge
0
5
ns
tdpd
PCLK negative edge to data output delay
0
5
ns
tsu
Data bus setup time
15
ns
thd
Data bus hold time
8
ns
VSYNC
D[9:0]
HREF
1050 x tline
21284tp
4 x tline
12396tp
240tp
tline = 1520tp
1280tp
Invalid Data
Row 1
Row 2
Row 1023
Row 0
P0 - P1279
VSYNC
D[9:0]
HREF
500 x tline
6402tp
4 x tline
6558tp
160tp
tline = 800tp
640tp
Invalid Data
Row 1
Row 2
Row 479
Row 0
P0 - P639
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